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@@ -90,9 +90,39 @@ pmu {
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/*
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* For HiFive Unmatched board. The encodings can be found here
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* https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
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+ * This example also binds standard SBI PMU hardware id's to U74 PMU event codes, U74 uses bitfield for
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+ * events encoding, so several U74 events can be bound to single perf id.
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+ * See SBI PMU hardware id's in include/sbi/sbi_ecall_interface.h
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*/
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pmu {
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compatible = "riscv,pmu";
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+ riscv,event-to-mhpmevent =
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+/* SBI_PMU_HW_CACHE_REFERENCES -> Instruction cache/ITIM busy | Data cache/DTIM busy */
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+ <0x00003 0x00000000 0x1801>,
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+/* SBI_PMU_HW_CACHE_MISSES -> Instruction cache miss | Data cache miss or memory-mapped I/O access */
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+ <0x00004 0x00000000 0x0302>,
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+/* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */
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+ <0x00005 0x00000000 0x4000>,
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+/* SBI_PMU_HW_BRANCH_MISSES -> Branch direction misprediction | Branch/jump target misprediction */
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+ <0x00006 0x00000000 0x6001>,
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+/* L1D_READ_MISS -> Data cache miss or memory-mapped I/O access */
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+ <0x10001 0x00000000 0x0202>,
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+/* L1D_WRITE_ACCESS -> Data cache write-back */
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+ <0x10002 0x00000000 0x0402>,
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+/* L1I_READ_ACCESS -> Instruction cache miss */
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+ <0x10009 0x00000000 0x0102>,
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+/* LL_READ_MISS -> UTLB miss */
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+ <0x10011 0x00000000 0x2002>,
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+/* DTLB_READ_MISS -> Data TLB miss */
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+ <0x10019 0x00000000 0x1002>,
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+/* ITLB_READ_MISS-> Instruction TLB miss */
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+ <0x10021 0x00000000 0x0802>;
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+ riscv,event-to-mhpmcounters = <0x00003 0x00006 0x18>,
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+ <0x10001 0x10002 0x18>,
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+ <0x10009 0x10009 0x18>,
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+ <0x10011 0x10011 0x18>,
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+ <0x10019 0x10019 0x18>,
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+ <0x10021 0x10021 0x18>;
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riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>,
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<0x0 0x1 0xffffffff 0xfff800ff 0x18>,
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<0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
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