0023-RISC-V-Also-invert-the-cond-move-condition-for-GEU-a.patch 1.6 KB

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  1. From 5dc6d2815b8e9c2e04dee20b422008e113d8ad02 Mon Sep 17 00:00:00 2001
  2. From: "Maciej W. Rozycki" <macro@embecosm.com>
  3. Date: Wed, 22 Nov 2023 01:18:25 +0000
  4. Subject: [PATCH 23/30] RISC-V: Also invert the cond-move condition for GEU and
  5. LEU
  6. Update `riscv_expand_conditional_move' and handle the missing GEU and
  7. LEU operators there, avoiding an extraneous conditional set operation,
  8. such as with this output:
  9. sgtu a0,a0,a1
  10. seqz a1,a0
  11. czero.eqz a3,a3,a1
  12. czero.nez a1,a2,a1
  13. or a0,a1,a3
  14. produced when optimizing for Zicond targets from:
  15. int
  16. movsigtu (int w, int x, int y, int z)
  17. {
  18. return w > x ? y : z;
  19. }
  20. These operators can be inverted producing optimal code such as this:
  21. sgtu a1,a0,a1
  22. czero.nez a3,a3,a1
  23. czero.eqz a1,a2,a1
  24. or a0,a1,a3
  25. which this change causes to happen.
  26. gcc/
  27. * config/riscv/riscv.cc (riscv_expand_conditional_move): Also
  28. invert the condition for GEU and LEU.
  29. ---
  30. gcc/config/riscv/riscv.cc | 5 ++++-
  31. 1 file changed, 4 insertions(+), 1 deletion(-)
  32. diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
  33. index 0a240d81cb3..cb2408b375d 100644
  34. --- a/gcc/config/riscv/riscv.cc
  35. +++ b/gcc/config/riscv/riscv.cc
  36. @@ -3588,7 +3588,10 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
  37. bool *invert_ptr = 0;
  38. bool invert = false;
  39. - if (code == LE || code == GE)
  40. + /* If riscv_expand_int_scc inverts the condition, then it will
  41. + flip the value of INVERT. We need to know where so that
  42. + we can adjust it for our needs. */
  43. + if (code == LE || code == LEU || code == GE || code == GEU)
  44. invert_ptr = &invert;
  45. /* Emit an scc like instruction into a temporary
  46. --
  47. 2.25.1