1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859 |
- From 5dc6d2815b8e9c2e04dee20b422008e113d8ad02 Mon Sep 17 00:00:00 2001
- From: "Maciej W. Rozycki" <macro@embecosm.com>
- Date: Wed, 22 Nov 2023 01:18:25 +0000
- Subject: [PATCH 23/30] RISC-V: Also invert the cond-move condition for GEU and
- LEU
- Update `riscv_expand_conditional_move' and handle the missing GEU and
- LEU operators there, avoiding an extraneous conditional set operation,
- such as with this output:
- sgtu a0,a0,a1
- seqz a1,a0
- czero.eqz a3,a3,a1
- czero.nez a1,a2,a1
- or a0,a1,a3
- produced when optimizing for Zicond targets from:
- int
- movsigtu (int w, int x, int y, int z)
- {
- return w > x ? y : z;
- }
- These operators can be inverted producing optimal code such as this:
- sgtu a1,a0,a1
- czero.nez a3,a3,a1
- czero.eqz a1,a2,a1
- or a0,a1,a3
- which this change causes to happen.
- gcc/
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Also
- invert the condition for GEU and LEU.
- ---
- gcc/config/riscv/riscv.cc | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
- diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
- index 0a240d81cb3..cb2408b375d 100644
- --- a/gcc/config/riscv/riscv.cc
- +++ b/gcc/config/riscv/riscv.cc
- @@ -3588,7 +3588,10 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
- bool *invert_ptr = 0;
- bool invert = false;
-
- - if (code == LE || code == GE)
- + /* If riscv_expand_int_scc inverts the condition, then it will
- + flip the value of INVERT. We need to know where so that
- + we can adjust it for our needs. */
- + if (code == LE || code == LEU || code == GE || code == GEU)
- invert_ptr = &invert;
-
- /* Emit an scc like instruction into a temporary
- --
- 2.25.1
|