0019-RISC-V-Add-Types-to-Un-Typed-Zicond-Instructions.patch 2.7 KB

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  1. From c55ea18c5a32ad138be9b4315c4f12751133485f Mon Sep 17 00:00:00 2001
  2. From: Edwin Lu <ewlu@rivosinc.com>
  3. Date: Mon, 11 Sep 2023 09:56:06 -0700
  4. Subject: [PATCH 19/30] RISC-V: Add Types to Un-Typed Zicond Instructions
  5. Creates a new "zicond" type and updates all zicond instructions
  6. with that type.
  7. gcc/ChangeLog:
  8. * config/riscv/riscv.md: Add "zicond" type
  9. * config/riscv/zicond.md: Update types
  10. Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
  11. ---
  12. gcc/config/riscv/riscv.md | 5 +++--
  13. gcc/config/riscv/zicond.md | 8 ++++----
  14. 2 files changed, 7 insertions(+), 6 deletions(-)
  15. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
  16. index 1b44a99c5f1..d965f4a2c5d 100644
  17. --- a/gcc/config/riscv/riscv.md
  18. +++ b/gcc/config/riscv/riscv.md
  19. @@ -248,6 +248,7 @@
  20. ;; atomic atomic instructions
  21. ;; condmove conditional moves
  22. ;; crypto cryptography instructions
  23. +;; zicond zicond instructions
  24. ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
  25. ;; rdvlenb vector byte length vlenb csrr read
  26. ;; rdvl vector length vl csrr read
  27. @@ -344,8 +345,8 @@
  28. "unknown,branch,jump,call,load,fpload,store,fpstore,
  29. mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
  30. fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
  31. - atomic,condmove,crypto,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
  32. - vldux,vldox,vstux,vstox,vldff,vldr,vstr,
  33. + zicond,atomic,condmove,crypto,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,
  34. + vlds,vsts,vldux,vldox,vstux,vstox,vldff,vldr,vstr,
  35. vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
  36. vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,
  37. vsalu,vaalu,vsmul,vsshift,vnclip,
  38. diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
  39. index 6627be3fa58..05e7348abba 100644
  40. --- a/gcc/config/riscv/zicond.md
  41. +++ b/gcc/config/riscv/zicond.md
  42. @@ -40,7 +40,7 @@
  43. else
  44. gcc_unreachable ();
  45. }
  46. -)
  47. +[(set_attr "type" "zicond")])
  48. (define_insn "*czero.<nez>.<GPR:mode><X:mode>"
  49. [(set (match_operand:GPR 0 "register_operand" "=r")
  50. @@ -57,7 +57,7 @@
  51. else
  52. gcc_unreachable ();
  53. }
  54. -)
  55. +[(set_attr "type" "zicond")])
  56. ;; Special optimization under eq/ne in primitive semantics
  57. (define_insn "*czero.eqz.<GPR:mode><X:mode>.opt1"
  58. @@ -75,7 +75,7 @@
  59. else
  60. gcc_unreachable ();
  61. }
  62. -)
  63. +[(set_attr "type" "zicond")])
  64. (define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
  65. [(set (match_operand:GPR 0 "register_operand" "=r")
  66. @@ -92,7 +92,7 @@
  67. else
  68. gcc_unreachable ();
  69. }
  70. -)
  71. +[(set_attr "type" "zicond")])
  72. ;; Combine creates this form in some cases (particularly the coremark
  73. ;; CRC loop).
  74. --
  75. 2.25.1