0018-RISC-V-Add-support-for-XVentanaCondOps-reusing-Zicon.patch 12 KB

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  1. From 75a5d45453f160d353dd5854d85bbb8494191df1 Mon Sep 17 00:00:00 2001
  2. From: Tsukasa OI <research_trasio@irq.a4lg.com>
  3. Date: Wed, 30 Aug 2023 02:34:35 +0000
  4. Subject: [PATCH 18/30] RISC-V: Add support for 'XVentanaCondOps' reusing
  5. 'Zicond' support
  6. 'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
  7. containing two instructions for conditional move and will be supported on
  8. their Veyron V1 CPU.
  9. And most notably (for historical reasons), 'XVentanaCondOps' and the
  10. standard 'Zicond' extension are functionally equivalent (only encodings and
  11. instruction names are different).
  12. * czero.eqz == vt.maskc
  13. * czero.nez == vt.maskcn
  14. This commit adds support for the 'XVentanaCondOps' extension by extending
  15. 'Zicond' extension support. With this, we can now reuse the optimization
  16. using the 'Zicond' extension for the 'XVentanaCondOps' extension.
  17. The specification for the 'XVentanaCondOps' extension is based on:
  18. <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf>
  19. gcc/ChangeLog:
  20. * common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
  21. Parse 'XVentanaCondOps' extension.
  22. * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
  23. (TARGET_XVENTANACONDOPS): Ditto.
  24. (TARGET_ZICOND_LIKE): New to represent targets with conditional
  25. moves like 'Zicond'. It includes RV64 + 'XVentanaCondOps'.
  26. * config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
  27. with TARGET_ZICOND_LIKE.
  28. (riscv_expand_conditional_move): Ditto.
  29. * config/riscv/riscv.md (mov<mode>cc): Replace TARGET_ZICOND with
  30. TARGET_ZICOND_LIKE.
  31. * config/riscv/riscv.opt: Add new riscv_xventana_subext.
  32. * config/riscv/zicond.md: Modify description.
  33. (eqz_ventana): New to match corresponding czero instructions.
  34. (nez_ventana): Ditto.
  35. (*czero.<eqz>.<GPR><X>): Emit a 'XVentanaCondOps' instruction if
  36. 'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
  37. (*czero.<eqz>.<GPR><X>): Ditto.
  38. (*czero.eqz.<GPR><X>.opt1): Ditto.
  39. (*czero.nez.<GPR><X>.opt2): Ditto.
  40. gcc/testsuite/ChangeLog:
  41. * gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
  42. * gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
  43. test to make sure that XVentanaCondOps instructions are disabled
  44. on RV32.
  45. * gcc.target/riscv/xventanacondops-xor-01.c: New test,
  46. ---
  47. gcc/common/config/riscv/riscv-common.cc | 2 +
  48. gcc/config/riscv/riscv-opts.h | 11 ++++
  49. gcc/config/riscv/riscv.cc | 4 +-
  50. gcc/config/riscv/riscv.md | 2 +-
  51. gcc/config/riscv/riscv.opt | 3 ++
  52. gcc/config/riscv/zicond.md | 53 +++++++++++++++----
  53. .../xventanacondops-primitiveSemantics-rv32.c | 8 +++
  54. .../xventanacondops-primitiveSemantics.c | 10 ++++
  55. .../gcc.target/riscv/xventanacondops-xor-01.c | 8 +++
  56. 9 files changed, 87 insertions(+), 14 deletions(-)
  57. create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
  58. create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
  59. create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
  60. diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
  61. index 27553ac168b..24e7af23c7c 100644
  62. --- a/gcc/common/config/riscv/riscv-common.cc
  63. +++ b/gcc/common/config/riscv/riscv-common.cc
  64. @@ -1283,6 +1283,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
  65. {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
  66. {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
  67. + {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS},
  68. +
  69. {NULL, NULL, 0}
  70. };
  71. diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
  72. index 0d82b7640de..5ad660574b7 100644
  73. --- a/gcc/config/riscv/riscv-opts.h
  74. +++ b/gcc/config/riscv/riscv-opts.h
  75. @@ -227,4 +227,15 @@ enum riscv_multilib_select_kind {
  76. #define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
  77. #define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
  78. +#define MASK_XVENTANACONDOPS (1 << 0)
  79. +
  80. +#define TARGET_XVENTANACONDOPS ((riscv_xventana_subext & MASK_XVENTANACONDOPS) != 0)
  81. +
  82. +#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
  83. +
  84. +/* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
  85. + is the highest priority choice and should not conflict with VLS modes. */
  86. +#define TARGET_VECTOR_VLS \
  87. + (TARGET_VECTOR && riscv_autovec_preference == RVV_SCALABLE)
  88. +
  89. #endif /* ! GCC_RISCV_OPTS_H */
  90. diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
  91. index 62d800bc459..14be2d7654a 100644
  92. --- a/gcc/config/riscv/riscv.cc
  93. +++ b/gcc/config/riscv/riscv.cc
  94. @@ -2344,7 +2344,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
  95. *total = COSTS_N_INSNS (1);
  96. return true;
  97. }
  98. - else if (TARGET_ZICOND
  99. + else if (TARGET_ZICOND_LIKE
  100. && outer_code == SET
  101. && ((GET_CODE (XEXP (x, 1)) == REG
  102. && XEXP (x, 2) == CONST0_RTX (GET_MODE (XEXP (x, 1))))
  103. @@ -3443,7 +3443,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
  104. cond, cons, alt)));
  105. return true;
  106. }
  107. - else if (TARGET_ZICOND
  108. + else if (TARGET_ZICOND_LIKE
  109. && GET_MODE_CLASS (mode) == MODE_INT)
  110. {
  111. /* The comparison must be comparing WORD_MODE objects. We must
  112. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
  113. index f810206f832..1b44a99c5f1 100644
  114. --- a/gcc/config/riscv/riscv.md
  115. +++ b/gcc/config/riscv/riscv.md
  116. @@ -2325,7 +2325,7 @@
  117. (if_then_else:GPR (match_operand 1 "comparison_operator")
  118. (match_operand:GPR 2 "sfb_alu_operand")
  119. (match_operand:GPR 3 "sfb_alu_operand")))]
  120. - "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND"
  121. + "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND_LIKE"
  122. {
  123. if (riscv_expand_conditional_move (operands[0], operands[1],
  124. operands[2], operands[3]))
  125. diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
  126. index bc5e63ab3e6..10228a8cffd 100644
  127. --- a/gcc/config/riscv/riscv.opt
  128. +++ b/gcc/config/riscv/riscv.opt
  129. @@ -238,6 +238,9 @@ int riscv_sv_subext
  130. TargetVariable
  131. int riscv_xthead_subext
  132. +TargetVariable
  133. +int riscv_xventana_subext
  134. +
  135. Enum
  136. Name(isa_spec_class) Type(enum riscv_isa_spec_class)
  137. Supported ISA specs (for use with the -misa-spec= option):
  138. diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
  139. index c28bee5d570..6627be3fa58 100644
  140. --- a/gcc/config/riscv/zicond.md
  141. +++ b/gcc/config/riscv/zicond.md
  142. @@ -1,4 +1,5 @@
  143. -;; Machine description for the RISC-V Zicond extension
  144. +;; Machine description for the RISC-V Zicond extension and functionally-
  145. +;; equivalent XVentanaCondOps vendor extension
  146. ;; Copyright (C) 2022-23 Free Software Foundation, Inc.
  147. ;; This file is part of GCC.
  148. @@ -20,16 +21,25 @@
  149. (define_code_iterator eq_or_ne [eq ne])
  150. (define_code_attr eqz [(eq "nez") (ne "eqz")])
  151. (define_code_attr nez [(eq "eqz") (ne "nez")])
  152. +(define_code_attr eqz_ventana [(eq "n") (ne "")])
  153. +(define_code_attr nez_ventana [(eq "") (ne "n")])
  154. -;; Zicond
  155. +;; Zicond / XVentanaCondOps
  156. (define_insn "*czero.<eqz>.<GPR:mode><X:mode>"
  157. [(set (match_operand:GPR 0 "register_operand" "=r")
  158. (if_then_else:GPR (eq_or_ne (match_operand:X 1 "register_operand" "r")
  159. (const_int 0))
  160. (match_operand:GPR 2 "register_operand" "r")
  161. (const_int 0)))]
  162. - "TARGET_ZICOND"
  163. - "czero.<eqz>\t%0,%2,%1"
  164. + "TARGET_ZICOND_LIKE"
  165. + {
  166. + if (TARGET_ZICOND)
  167. + return "czero.<eqz>\t%0,%2,%1";
  168. + else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
  169. + return "vt.maskc<eqz_ventana>\t%0,%2,%1";
  170. + else
  171. + gcc_unreachable ();
  172. + }
  173. )
  174. (define_insn "*czero.<nez>.<GPR:mode><X:mode>"
  175. @@ -38,8 +48,15 @@
  176. (const_int 0))
  177. (const_int 0)
  178. (match_operand:GPR 2 "register_operand" "r")))]
  179. - "TARGET_ZICOND"
  180. - "czero.<nez>\t%0,%2,%1"
  181. + "TARGET_ZICOND_LIKE"
  182. + {
  183. + if (TARGET_ZICOND)
  184. + return "czero.<nez>\t%0,%2,%1";
  185. + else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
  186. + return "vt.maskc<nez_ventana>\t%0,%2,%1";
  187. + else
  188. + gcc_unreachable ();
  189. + }
  190. )
  191. ;; Special optimization under eq/ne in primitive semantics
  192. @@ -49,8 +66,15 @@
  193. (const_int 0))
  194. (match_operand:GPR 2 "register_operand" "1")
  195. (match_operand:GPR 3 "register_operand" "r")))]
  196. - "TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])"
  197. - "czero.eqz\t%0,%3,%1"
  198. + "TARGET_ZICOND_LIKE && rtx_equal_p (operands[1], operands[2])"
  199. + {
  200. + if (TARGET_ZICOND)
  201. + return "czero.eqz\t%0,%3,%1";
  202. + else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
  203. + return "vt.maskc\t%0,%3,%1";
  204. + else
  205. + gcc_unreachable ();
  206. + }
  207. )
  208. (define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
  209. @@ -60,7 +84,14 @@
  210. (match_operand:GPR 2 "register_operand" "r")
  211. (match_operand:GPR 3 "register_operand" "1")))]
  212. "TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])"
  213. - "czero.eqz\t%0,%2,%1"
  214. + {
  215. + if (TARGET_ZICOND)
  216. + return "czero.eqz\t%0,%2,%1";
  217. + else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
  218. + return "vt.maskc\t%0,%2,%1";
  219. + else
  220. + gcc_unreachable ();
  221. + }
  222. )
  223. ;; Combine creates this form in some cases (particularly the coremark
  224. @@ -72,7 +103,7 @@
  225. (match_operand 2 "immediate_operand"))
  226. (match_operand:X 3 "register_operand")))
  227. (clobber (match_operand:X 4 "register_operand"))]
  228. - "TARGET_ZICOND && TARGET_ZBS"
  229. + "TARGET_ZICOND_LIKE && TARGET_ZBS"
  230. [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
  231. (set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0))
  232. (const_int 0)
  233. @@ -85,7 +116,7 @@
  234. (match_operand 2 "immediate_operand"))
  235. (match_operand:X 3 "register_operand")))
  236. (clobber (match_operand:X 4 "register_operand"))]
  237. - "TARGET_ZICOND && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
  238. + "TARGET_ZICOND_LIKE && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
  239. [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
  240. (set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0))
  241. (const_int 0)
  242. diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
  243. new file mode 100644
  244. index 00000000000..862ad309b52
  245. --- /dev/null
  246. +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
  247. @@ -0,0 +1,8 @@
  248. +/* { dg-do compile } */
  249. +/* { dg-options "-march=rv32gc_xventanacondops -mabi=ilp32d" } */
  250. +/* { dg-skip-if "" { *-*-* } {"-O0" "-Og"} } */
  251. +
  252. +#include "zicond-primitiveSemantics.c"
  253. +
  254. +/* { dg-final { scan-assembler-not "vt\\.maskc\t" } } */
  255. +/* { dg-final { scan-assembler-not "vt\\.maskcn\t" } } */
  256. diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
  257. new file mode 100644
  258. index 00000000000..644ca12d647
  259. --- /dev/null
  260. +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
  261. @@ -0,0 +1,10 @@
  262. +/* { dg-do compile } */
  263. +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */
  264. +/* { dg-skip-if "" { *-*-* } {"-O0" "-Og"} } */
  265. +
  266. +#include "zicond-primitiveSemantics.c"
  267. +
  268. +/* { dg-final { scan-assembler-times "vt\\.maskc\t" 6 } } */
  269. +/* { dg-final { scan-assembler-times "vt\\.maskcn\t" 6 } } */
  270. +/* { dg-final { scan-assembler-not "beq" } } */
  271. +/* { dg-final { scan-assembler-not "bne" } } */
  272. diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
  273. new file mode 100644
  274. index 00000000000..634eff84f89
  275. --- /dev/null
  276. +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
  277. @@ -0,0 +1,8 @@
  278. +/* { dg-do compile } */
  279. +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */
  280. +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
  281. +
  282. +#include "zicond-xor-01.c"
  283. +
  284. +/* { dg-final { scan-assembler-times "vt\\.maskc\t" 1 } } */
  285. +/* { dg-final { scan-assembler-times "xor\t" 1 } } */
  286. --
  287. 2.25.1