0012-committed-RISC-V-Fix-bug-in-condition-canonicalizati.patch 2.3 KB

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  1. From 0f311b02572bb49982871a295dc1512bb6133a90 Mon Sep 17 00:00:00 2001
  2. From: Jeff Law <jlaw@ventanamicro.com>
  3. Date: Tue, 8 Aug 2023 15:32:38 -0600
  4. Subject: [PATCH 12/30] [committed] [RISC-V] Fix bug in condition
  5. canonicalization for zicond
  6. Vineet's glibc build triggered an ICE building glibc with the latest zicond
  7. bits. It's a minor issue in the canonicalization of the condition.
  8. When we need to canonicalize the condition we use an SCC insn to handle the
  9. primary comparison with the output going into a temporary with the final value
  10. of 0/1 which we can then use in a zicond instruction.
  11. The mode of the newly generated temporary was taken from mode of the final
  12. destination. That's simply wrong. The mode of the condition needs to be
  13. word_mode.
  14. This patch fixes that minor problem and adds a suitable testcase.
  15. gcc/
  16. * config/riscv/riscv.cc (riscv_expand_conditional_move): Use word_mode
  17. for the temporary when canonicalizing the condition.
  18. gcc/testsuite
  19. * gcc.target/riscv/zicond-ice-1.c: New test.
  20. ---
  21. gcc/config/riscv/riscv.cc | 2 +-
  22. gcc/testsuite/gcc.target/riscv/zicond-ice-1.c | 13 +++++++++++++
  23. 2 files changed, 14 insertions(+), 1 deletion(-)
  24. create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ice-1.c
  25. diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
  26. index 9b9fff496a3..7488ffbe680 100644
  27. --- a/gcc/config/riscv/riscv.cc
  28. +++ b/gcc/config/riscv/riscv.cc
  29. @@ -3467,7 +3467,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
  30. /* Emit an scc like instruction into a temporary
  31. so that we can use an EQ/NE comparison. */
  32. - rtx tmp = gen_reg_rtx (mode);
  33. + rtx tmp = gen_reg_rtx (word_mode);
  34. /* We can support both FP and integer conditional moves. */
  35. if (INTEGRAL_MODE_P (GET_MODE (XEXP (op, 0))))
  36. diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-1.c b/gcc/testsuite/gcc.target/riscv/zicond-ice-1.c
  37. new file mode 100644
  38. index 00000000000..d1f98a42582
  39. --- /dev/null
  40. +++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-1.c
  41. @@ -0,0 +1,13 @@
  42. +/* { dg-do compile } */
  43. +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
  44. +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */
  45. +
  46. +int a, c;
  47. +long b;
  48. +
  49. +void
  50. +d() {
  51. + for (;;)
  52. + if (a & (b < 8 ?: 1 << b))
  53. + c = 1;
  54. +}
  55. --
  56. 2.25.1