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- From 0f311b02572bb49982871a295dc1512bb6133a90 Mon Sep 17 00:00:00 2001
- From: Jeff Law <jlaw@ventanamicro.com>
- Date: Tue, 8 Aug 2023 15:32:38 -0600
- Subject: [PATCH 12/30] [committed] [RISC-V] Fix bug in condition
- canonicalization for zicond
- Vineet's glibc build triggered an ICE building glibc with the latest zicond
- bits. It's a minor issue in the canonicalization of the condition.
- When we need to canonicalize the condition we use an SCC insn to handle the
- primary comparison with the output going into a temporary with the final value
- of 0/1 which we can then use in a zicond instruction.
- The mode of the newly generated temporary was taken from mode of the final
- destination. That's simply wrong. The mode of the condition needs to be
- word_mode.
- This patch fixes that minor problem and adds a suitable testcase.
- gcc/
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Use word_mode
- for the temporary when canonicalizing the condition.
- gcc/testsuite
- * gcc.target/riscv/zicond-ice-1.c: New test.
- ---
- gcc/config/riscv/riscv.cc | 2 +-
- gcc/testsuite/gcc.target/riscv/zicond-ice-1.c | 13 +++++++++++++
- 2 files changed, 14 insertions(+), 1 deletion(-)
- create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ice-1.c
- diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
- index 9b9fff496a3..7488ffbe680 100644
- --- a/gcc/config/riscv/riscv.cc
- +++ b/gcc/config/riscv/riscv.cc
- @@ -3467,7 +3467,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
-
- /* Emit an scc like instruction into a temporary
- so that we can use an EQ/NE comparison. */
- - rtx tmp = gen_reg_rtx (mode);
- + rtx tmp = gen_reg_rtx (word_mode);
-
- /* We can support both FP and integer conditional moves. */
- if (INTEGRAL_MODE_P (GET_MODE (XEXP (op, 0))))
- diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-1.c b/gcc/testsuite/gcc.target/riscv/zicond-ice-1.c
- new file mode 100644
- index 00000000000..d1f98a42582
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-1.c
- @@ -0,0 +1,13 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
- +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */
- +
- +int a, c;
- +long b;
- +
- +void
- +d() {
- + for (;;)
- + if (a & (b < 8 ?: 1 << b))
- + c = 1;
- +}
- --
- 2.25.1
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