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- From 34431e4c3af4140bdc3fcf57039e5f172b3215d4 Mon Sep 17 00:00:00 2001
- From: Jeff Law <jeffreyalaw@gmail.com>
- Date: Thu, 3 Aug 2023 10:57:23 -0400
- Subject: [PATCH 08/30] [committed][RISC-V] Remove errant hunk of code
- I'm using this hunk locally to more thoroughly exercise the zicond paths
- due to inaccuracies elsewhere in the costing model. It was never
- supposed to be part of the costing commit though. And as we've seen
- it's causing problems with the vector bits.
- While my testing isn't complete, this hunk was never supposed to be
- pushed and it's causing problems. So I'm just ripping it out.
- There's a bigger TODO in this space WRT a top-to-bottom evaluation of
- the costing on RISC-V. I'm still formulating what that evaluation is
- going to look like, so don't hold your breath waiting on it.
- Pushed to the trunk.
- gcc/
- * config/riscv/riscv.cc (riscv_rtx_costs): Remove errant hunk from
- recent commit.
- ---
- gcc/config/riscv/riscv.cc | 10 ----------
- 1 file changed, 10 deletions(-)
- diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
- index 6ec985db430..dca9329608f 100644
- --- a/gcc/config/riscv/riscv.cc
- +++ b/gcc/config/riscv/riscv.cc
- @@ -2749,16 +2749,6 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
- }
- return false;
-
- - case SET:
- - /* A simple SET with a register destination takes its cost solely from
- - the SET_SRC operand. */
- - if (outer_code == INSN && REG_P (SET_DEST (x)))
- - {
- - *total = riscv_rtx_costs (SET_SRC (x), mode, SET, opno, total, speed);
- - return true;
- - }
- - return false;
- -
- default:
- return false;
- }
- --
- 2.25.1
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