0004-PATCH-3-5-RISC-V-RISC-V-Conditional-Move-costing-was.patch 2.6 KB

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  1. From a816152333d91e47d8ac6bf3778c57dbbdc705e8 Mon Sep 17 00:00:00 2001
  2. From: Xiao Zeng <zengxiao@eswincomputing.com>
  3. Date: Mon, 31 Jul 2023 12:26:51 -0600
  4. Subject: [PATCH 04/30] [PATCH 3/5] [RISC-V] RISC-V Conditional Move costing
  5. [was:Generate Zicond instruction for select pattern with condition eq or neq
  6. to 0]
  7. This provides some basic costing to conditional moves. The underlying
  8. primitive of an IF-THEN-ELSE which turns into czero is a single insn
  9. (COSTS_N_INSNS (1)).
  10. But these insns were still consistently showing up with the wrong cost (8
  11. instead of 4). This was chased down to computing the cost of the destination
  12. and the cost of the source independently, then summing them. That seems
  13. horribly wrong for register destinations. So this patch special cases
  14. an INSN that is just a SET of a register destination so that the cost
  15. comes from the SET_SRC.
  16. Long term the whole costing model needs a review.
  17. gcc/
  18. * config/riscv/riscv.cc (riscv_rtx_costs, case IF_THEN_ELSE): Add
  19. Zicond costing.
  20. (case SET): For INSNs that just set a REG, take the cost from the
  21. SET_SRC.
  22. Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
  23. ---
  24. gcc/config/riscv/riscv.cc | 24 ++++++++++++++++++++++++
  25. 1 file changed, 24 insertions(+)
  26. diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
  27. index 9c626904e89..e95cb2db24c 100644
  28. --- a/gcc/config/riscv/riscv.cc
  29. +++ b/gcc/config/riscv/riscv.cc
  30. @@ -2344,6 +2344,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
  31. *total = COSTS_N_INSNS (1);
  32. return true;
  33. }
  34. + else if (TARGET_ZICOND
  35. + && outer_code == SET
  36. + && ((GET_CODE (XEXP (x, 1)) == REG
  37. + && XEXP (x, 2) == CONST0_RTX (GET_MODE (XEXP (x, 1))))
  38. + || (GET_CODE (XEXP (x, 2)) == REG
  39. + && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 2))))
  40. + || (GET_CODE (XEXP (x, 1)) == REG
  41. + && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0)))
  42. + || (GET_CODE (XEXP (x, 1)) == REG
  43. + && rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0)))))
  44. + {
  45. + *total = COSTS_N_INSNS (1);
  46. + return true;
  47. + }
  48. else if (LABEL_REF_P (XEXP (x, 1)) && XEXP (x, 2) == pc_rtx)
  49. {
  50. if (equality_operator (XEXP (x, 0), mode)
  51. @@ -2721,6 +2735,16 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
  52. }
  53. return false;
  54. + case SET:
  55. + /* A simple SET with a register destination takes its cost solely from
  56. + the SET_SRC operand. */
  57. + if (outer_code == INSN && REG_P (SET_DEST (x)))
  58. + {
  59. + *total = riscv_rtx_costs (SET_SRC (x), mode, SET, opno, total, speed);
  60. + return true;
  61. + }
  62. + return false;
  63. +
  64. default:
  65. return false;
  66. }
  67. --
  68. 2.25.1