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- From 01be575a5f6a894d41f16d6531aec88fc66f6c28 Mon Sep 17 00:00:00 2001
- From: Xiao Zeng <zengxiao@eswincomputing.com>
- Date: Wed, 26 Jul 2023 10:07:42 -0600
- Subject: [PATCH 02/30] [PATCH 1/5] [RISC-V] Recognize Zicond extension
- gcc/ChangeLog:
- * common/config/riscv/riscv-common.cc: New extension.
- * config/riscv/riscv-opts.h (MASK_ZICOND): New mask.
- (TARGET_ZICOND): New target.
- gcc/testsuite/ChangeLog:
- * gcc.target/riscv/attribute-20.c: New test.
- * gcc.target/riscv/attribute-21.c: New test.
- Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
- ---
- gcc/common/config/riscv/riscv-common.cc | 3 +++
- gcc/config/riscv/riscv-opts.h | 3 +++
- gcc/testsuite/gcc.target/riscv/attribute-20.c | 6 ++++++
- gcc/testsuite/gcc.target/riscv/attribute-21.c | 6 ++++++
- 4 files changed, 18 insertions(+)
- create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-20.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-21.c
- diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
- index 68c2e843b4e..27553ac168b 100644
- --- a/gcc/common/config/riscv/riscv-common.cc
- +++ b/gcc/common/config/riscv/riscv-common.cc
- @@ -163,6 +163,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
- {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
- {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
-
- + {"zicond", ISA_SPEC_CLASS_NONE, 1, 0},
- +
- {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
-
- {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
- @@ -1201,6 +1203,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
-
- {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
- {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
- + {"zicond", &gcc_options::x_riscv_zi_subext, MASK_ZICOND},
-
- {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
-
- diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
- index be8de182312..0d82b7640de 100644
- --- a/gcc/config/riscv/riscv-opts.h
- +++ b/gcc/config/riscv/riscv-opts.h
- @@ -175,6 +175,9 @@ enum riscv_multilib_select_kind {
- #define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
- #define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
-
- +#define MASK_ZICOND (1 << 2)
- +#define TARGET_ZICOND ((riscv_zi_subext & MASK_ZICOND) != 0)
- +
- #define MASK_ZFHMIN (1 << 0)
- #define MASK_ZFH (1 << 1)
-
- diff --git a/gcc/testsuite/gcc.target/riscv/attribute-20.c b/gcc/testsuite/gcc.target/riscv/attribute-20.c
- new file mode 100644
- index 00000000000..b69c36cf4f1
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/attribute-20.c
- @@ -0,0 +1,6 @@
- +/* { dg-do compile } */
- +/* { dg-options "-mriscv-attribute -march=rv32i_zicond -mabi=ilp32" } */
- +
- +void foo(){}
- +
- +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_zicond1p0\"" } } */
- diff --git a/gcc/testsuite/gcc.target/riscv/attribute-21.c b/gcc/testsuite/gcc.target/riscv/attribute-21.c
- new file mode 100644
- index 00000000000..160312a0d48
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/attribute-21.c
- @@ -0,0 +1,6 @@
- +/* { dg-do compile } */
- +/* { dg-options "-mriscv-attribute -march=rv64i_zicond -mabi=lp64" } */
- +
- +void foo(){}
- +
- +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicond1p0\"" } } */
- --
- 2.25.1
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