0002-PATCH-1-5-RISC-V-Recognize-Zicond-extension.patch 3.2 KB

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  1. From 01be575a5f6a894d41f16d6531aec88fc66f6c28 Mon Sep 17 00:00:00 2001
  2. From: Xiao Zeng <zengxiao@eswincomputing.com>
  3. Date: Wed, 26 Jul 2023 10:07:42 -0600
  4. Subject: [PATCH 02/30] [PATCH 1/5] [RISC-V] Recognize Zicond extension
  5. gcc/ChangeLog:
  6. * common/config/riscv/riscv-common.cc: New extension.
  7. * config/riscv/riscv-opts.h (MASK_ZICOND): New mask.
  8. (TARGET_ZICOND): New target.
  9. gcc/testsuite/ChangeLog:
  10. * gcc.target/riscv/attribute-20.c: New test.
  11. * gcc.target/riscv/attribute-21.c: New test.
  12. Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
  13. ---
  14. gcc/common/config/riscv/riscv-common.cc | 3 +++
  15. gcc/config/riscv/riscv-opts.h | 3 +++
  16. gcc/testsuite/gcc.target/riscv/attribute-20.c | 6 ++++++
  17. gcc/testsuite/gcc.target/riscv/attribute-21.c | 6 ++++++
  18. 4 files changed, 18 insertions(+)
  19. create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-20.c
  20. create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-21.c
  21. diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
  22. index 68c2e843b4e..27553ac168b 100644
  23. --- a/gcc/common/config/riscv/riscv-common.cc
  24. +++ b/gcc/common/config/riscv/riscv-common.cc
  25. @@ -163,6 +163,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
  26. {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
  27. {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
  28. + {"zicond", ISA_SPEC_CLASS_NONE, 1, 0},
  29. +
  30. {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
  31. {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
  32. @@ -1201,6 +1203,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
  33. {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
  34. {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
  35. + {"zicond", &gcc_options::x_riscv_zi_subext, MASK_ZICOND},
  36. {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
  37. diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
  38. index be8de182312..0d82b7640de 100644
  39. --- a/gcc/config/riscv/riscv-opts.h
  40. +++ b/gcc/config/riscv/riscv-opts.h
  41. @@ -175,6 +175,9 @@ enum riscv_multilib_select_kind {
  42. #define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
  43. #define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
  44. +#define MASK_ZICOND (1 << 2)
  45. +#define TARGET_ZICOND ((riscv_zi_subext & MASK_ZICOND) != 0)
  46. +
  47. #define MASK_ZFHMIN (1 << 0)
  48. #define MASK_ZFH (1 << 1)
  49. diff --git a/gcc/testsuite/gcc.target/riscv/attribute-20.c b/gcc/testsuite/gcc.target/riscv/attribute-20.c
  50. new file mode 100644
  51. index 00000000000..b69c36cf4f1
  52. --- /dev/null
  53. +++ b/gcc/testsuite/gcc.target/riscv/attribute-20.c
  54. @@ -0,0 +1,6 @@
  55. +/* { dg-do compile } */
  56. +/* { dg-options "-mriscv-attribute -march=rv32i_zicond -mabi=ilp32" } */
  57. +
  58. +void foo(){}
  59. +
  60. +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_zicond1p0\"" } } */
  61. diff --git a/gcc/testsuite/gcc.target/riscv/attribute-21.c b/gcc/testsuite/gcc.target/riscv/attribute-21.c
  62. new file mode 100644
  63. index 00000000000..160312a0d48
  64. --- /dev/null
  65. +++ b/gcc/testsuite/gcc.target/riscv/attribute-21.c
  66. @@ -0,0 +1,6 @@
  67. +/* { dg-do compile } */
  68. +/* { dg-options "-mriscv-attribute -march=rv64i_zicond -mabi=lp64" } */
  69. +
  70. +void foo(){}
  71. +
  72. +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicond1p0\"" } } */
  73. --
  74. 2.25.1