0001-add-customer-pref-support.patch 6.2 KB

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  1. From ed52ba73f555c0a103e10f18127864e390c98443 Mon Sep 17 00:00:00 2001
  2. From: "max.ma" <max.ma@starfivetech.com>
  3. Date: Mon, 5 Sep 2022 01:17:31 -0700
  4. Subject: [PATCH 1/2] add customer pref support
  5. ---
  6. gas/config/tc-riscv.c | 44 +++++++++++++++++++++++++++++++++++++-
  7. include/opcode/riscv-opc.h | 1 +
  8. include/opcode/riscv.h | 9 ++++++++
  9. opcodes/riscv-dis.c | 10 +++++++++
  10. opcodes/riscv-opc.c | 1 +
  11. 5 files changed, 64 insertions(+), 1 deletion(-)
  12. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  13. index 297bb9b2a81..e995cbf6417 100644
  14. --- a/gas/config/tc-riscv.c
  15. +++ b/gas/config/tc-riscv.c
  16. @@ -1354,7 +1354,9 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
  17. case ')': break;
  18. case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
  19. case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
  20. - case 'A': break; /* Macro operand, must be symbol. */
  21. + case '#': used_bits |= ENCODE_PREF_TIMM (-1U); break;
  22. + case '+': used_bits |= ENCODE_PREF_SIMM (-1U); break;
  23. + case 'A': break; /* Macro operand, must be symbol. */
  24. case 'B': break; /* Macro operand, must be symbol or constant. */
  25. case 'c': break; /* Macro operand, must be symbol or constant. */
  26. case 'I': break; /* Macro operand, must be constant. */
  27. @@ -1803,6 +1805,27 @@ check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
  28. normalize_constant_expr (ex);
  29. }
  30. +/* The pref type should be one of the following:
  31. + 0000 - scalar prefetch L1, fetch data as if for a normal scalar load,
  32. + and imply load into all lower cache destination levels.
  33. + 0001 - scalar prefetch L2, fetch data and place the cache-line into L2,
  34. + and imply load into all lower cache destination levels.
  35. + 0010 - scalar prefetch L3, fetch data and place the cache-line into L3,
  36. + and imply load into all lower cache destination levels.
  37. + 0011 - scalar prefetch L4, fetch data and place the cache-line into L4,
  38. + and imply load into all lower cache destination levels
  39. + (if the L5 is in the cache heirarchy).
  40. + 1000 - vector prefetch L1, fetch data as if for a normal scalar load
  41. + but place the cache-line into vector buffer (vector L1) ,
  42. + and imply load into all lower cache destination levels.
  43. +*/
  44. +
  45. +static bfd_boolean check_pref_type(unsigned long type)
  46. +{
  47. + if (type != 0 && type != 1 && type != 2 && type != 3 && type != 8)
  48. + as_bad (_("Improper pref type (%lu)"), type);
  49. +}
  50. +
  51. static symbolS *
  52. make_internal_label (void)
  53. {
  54. @@ -3165,6 +3188,25 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
  55. asarg = expr_parse_end;
  56. continue;
  57. + case '#':
  58. + my_getExpression (imm_expr, asarg);
  59. + check_pref_type((unsigned long)imm_expr->X_add_number);
  60. + INSERT_OPERAND (PREF_TYPE, *ip, imm_expr->X_add_number);
  61. + imm_expr->X_op = O_absent;
  62. + asarg = expr_end;
  63. + continue;
  64. +
  65. + case '+':
  66. + my_getExpression (imm_expr, asarg);
  67. + check_absolute_expr (ip, imm_expr, FALSE);
  68. + if (imm_expr->X_add_number > 127 || imm_expr->X_add_number < -128)
  69. + as_bad (_("Improper pref offset value (%d)"),
  70. + (long) imm_expr->X_add_number);
  71. + INSERT_OPERAND (PREF_OFFSET, *ip, imm_expr->X_add_number);
  72. + imm_expr->X_op = O_absent;
  73. + asarg = expr_end;
  74. + continue;
  75. +
  76. case 'E': /* Control register. */
  77. insn_with_csr = true;
  78. explicit_priv_attr = true;
  79. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  80. index 90f44153750..07d5a11f733 100644
  81. --- a/include/opcode/riscv-opc.h
  82. +++ b/include/opcode/riscv-opc.h
  83. @@ -255,6 +255,7 @@
  84. #define MASK_SFENCE_VMA 0xfe007fff
  85. #define MATCH_WFI 0x10500073
  86. #define MASK_WFI 0xffffffff
  87. +#define MASK_CUSTOMER_PREF 0x7fff
  88. #define MATCH_CSRRW 0x1073
  89. #define MASK_CSRRW 0x707f
  90. #define MATCH_CSRRS 0x2073
  91. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
  92. index d859f44fc92..40ae251ae3c 100644
  93. --- a/include/opcode/riscv.h
  94. +++ b/include/opcode/riscv.h
  95. @@ -153,6 +153,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
  96. (RV_X(x, 0, 10) << 20)
  97. #define ENCODE_RVV_VC_IMM(x) \
  98. (RV_X(x, 0, 11) << 20)
  99. +#define ENCODE_PREF_TIMM(x) \
  100. + (RV_X(x, 0, 4) << 20)
  101. +#define ENCODE_PREF_SIMM(x) \
  102. + (RV_X(x, 0, 8) << 24)
  103. #define ENCODE_RVV_VI_UIMM6(x) \
  104. (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)
  105. @@ -255,6 +259,11 @@ static inline unsigned int riscv_insn_length (insn_t insn)
  106. #define OP_MASK_FUNCT2 0x3
  107. #define OP_SH_FUNCT2 25
  108. +#define OP_MASK_PREF_TYPE 0x0f
  109. +#define OP_SH_PREF_TYPE 20
  110. +#define OP_MASK_PREF_OFFSET 0xff
  111. +#define OP_SH_PREF_OFFSET 24
  112. +
  113. /* RVC fields. */
  114. #define OP_MASK_OP2 0x3
  115. diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
  116. index 827d9b67437..3bb530a632c 100644
  117. --- a/opcodes/riscv-dis.c
  118. +++ b/opcodes/riscv-dis.c
  119. @@ -519,6 +519,16 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
  120. (unsigned)EXTRACT_OPERAND (SHAMTW, l));
  121. break;
  122. + case '#':
  123. + print (info->stream, dis_style_immediate, "0x%x",
  124. + (int)EXTRACT_OPERAND (PREF_TYPE, l));
  125. + break;
  126. +
  127. + case '+':
  128. + print (info->stream, dis_style_immediate, "0x%x",
  129. + (int)EXTRACT_OPERAND (PREF_OFFSET, l));
  130. + break;
  131. +
  132. case 'S':
  133. case 'U':
  134. print (info->stream, dis_style_register, "%s", riscv_fpr_names[rs1]);
  135. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  136. index 533e3f4a079..985e2d1b275 100644
  137. --- a/opcodes/riscv-opc.c
  138. +++ b/opcodes/riscv-opc.c
  139. @@ -470,6 +470,7 @@ const struct riscv_opcode riscv_opcodes[] =
  140. {"snez", 0, INSN_CLASS_I, "d,t", MATCH_SLTU, MASK_SLTU|MASK_RS1, match_opcode, INSN_ALIAS },
  141. {"sltz", 0, INSN_CLASS_I, "d,s", MATCH_SLT, MASK_SLT|MASK_RS2, match_opcode, INSN_ALIAS },
  142. {"sgtz", 0, INSN_CLASS_I, "d,t", MATCH_SLT, MASK_SLT|MASK_RS1, match_opcode, INSN_ALIAS },
  143. +{"pref", 0, INSN_CLASS_I, "#,+(s)", MATCH_SLTI, MASK_CUSTOMER_PREF, match_opcode, INSN_ALIAS },
  144. {"slti", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
  145. {"slt", 0, INSN_CLASS_I, "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 },
  146. {"slt", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
  147. --
  148. 2.25.1