0016-Rename-some-assembler-mnemonic-for-rvv1.0.patch 5.6 KB

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  1. From c9ff2e904f6646338b50dc7b4b7b4116066780a4 Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Thu, 7 Apr 2022 14:42:34 +0800
  4. Subject: [PATCH 16/18] Rename some assembler mnemonic for rvv1.0
  5. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  6. ---
  7. gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d | 12 ++++++------
  8. gas/testsuite/gas/riscv/vector-insns.d | 8 ++++----
  9. opcodes/riscv-opc.c | 9 ++++++---
  10. 3 files changed, 16 insertions(+), 13 deletions(-)
  11. diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
  12. index 207a410c28..1e050f14ba 100644
  13. --- a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
  14. +++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
  15. @@ -12,18 +12,18 @@ Disassembly of section .text:
  16. [ ]+[0-9a-f]+:[ ]+6cc64457[ ]+vmslt.vx[ ]+v8,v12,a2,v0.t
  17. [ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0
  18. [ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t
  19. -[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12
  20. +[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandn.mm[ ]+v0,v0,v12
  21. [ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t
  22. -[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12
  23. -[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0
  24. +[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandn.mm[ ]+v12,v0,v12
  25. +[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandn.mm[ ]+v4,v4,v0
  26. [ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4
  27. [ ]+[0-9a-f]+:[ ]+6a85c257[ ]+vmsltu.vx[ ]+v4,v8,a1
  28. [ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4
  29. [ ]+[0-9a-f]+:[ ]+68c64457[ ]+vmsltu.vx[ ]+v8,v12,a2,v0.t
  30. [ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0
  31. [ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t
  32. -[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12
  33. +[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandn.mm[ ]+v0,v0,v12
  34. [ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t
  35. -[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12
  36. -[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0
  37. +[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandn.mm[ ]+v12,v0,v12
  38. +[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandn.mm[ ]+v4,v4,v0
  39. [ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4
  40. diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
  41. index f09d139b83..92a61185ca 100644
  42. --- a/gas/testsuite/gas/riscv/vector-insns.d
  43. +++ b/gas/testsuite/gas/riscv/vector-insns.d
  44. @@ -1883,20 +1883,20 @@ Disassembly of section .text:
  45. [ ]+[0-9a-f]+:[ ]+76842257[ ]+vmnot.m[ ]+v4,v8
  46. [ ]+[0-9a-f]+:[ ]+66862257[ ]+vmand.mm[ ]+v4,v8,v12
  47. [ ]+[0-9a-f]+:[ ]+76862257[ ]+vmnand.mm[ ]+v4,v8,v12
  48. -[ ]+[0-9a-f]+:[ ]+62862257[ ]+vmandnot.mm[ ]+v4,v8,v12
  49. +[ ]+[0-9a-f]+:[ ]+62862257[ ]+vmandn.mm[ ]+v4,v8,v12
  50. [ ]+[0-9a-f]+:[ ]+6e862257[ ]+vmxor.mm[ ]+v4,v8,v12
  51. [ ]+[0-9a-f]+:[ ]+6a862257[ ]+vmor.mm[ ]+v4,v8,v12
  52. [ ]+[0-9a-f]+:[ ]+7a862257[ ]+vmnor.mm[ ]+v4,v8,v12
  53. -[ ]+[0-9a-f]+:[ ]+72862257[ ]+vmornot.mm[ ]+v4,v8,v12
  54. +[ ]+[0-9a-f]+:[ ]+72862257[ ]+vmorn.mm[ ]+v4,v8,v12
  55. [ ]+[0-9a-f]+:[ ]+7e862257[ ]+vmxnor.mm[ ]+v4,v8,v12
  56. -[ ]+[0-9a-f]+:[ ]+42c82557[ ]+vpopc.m[ ]+a0,v12
  57. +[ ]+[0-9a-f]+:[ ]+42c82557[ ]+vcpop.m[ ]+a0,v12
  58. [ ]+[0-9a-f]+:[ ]+42c8a557[ ]+vfirst.m[ ]+a0,v12
  59. [ ]+[0-9a-f]+:[ ]+5280a257[ ]+vmsbf.m[ ]+v4,v8
  60. [ ]+[0-9a-f]+:[ ]+5281a257[ ]+vmsif.m[ ]+v4,v8
  61. [ ]+[0-9a-f]+:[ ]+52812257[ ]+vmsof.m[ ]+v4,v8
  62. [ ]+[0-9a-f]+:[ ]+52882257[ ]+viota.m[ ]+v4,v8
  63. [ ]+[0-9a-f]+:[ ]+5208a257[ ]+vid.v[ ]+v4
  64. -[ ]+[0-9a-f]+:[ ]+40c82557[ ]+vpopc.m[ ]+a0,v12,v0.t
  65. +[ ]+[0-9a-f]+:[ ]+40c82557[ ]+vcpop.m[ ]+a0,v12,v0.t
  66. [ ]+[0-9a-f]+:[ ]+40c8a557[ ]+vfirst.m[ ]+a0,v12,v0.t
  67. [ ]+[0-9a-f]+:[ ]+5080a257[ ]+vmsbf.m[ ]+v4,v8,v0.t
  68. [ ]+[0-9a-f]+:[ ]+5081a257[ ]+vmsif.m[ ]+v4,v8,v0.t
  69. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  70. index f42a0db494..a2c782309c 100644
  71. --- a/opcodes/riscv-opc.c
  72. +++ b/opcodes/riscv-opc.c
  73. @@ -2043,14 +2043,17 @@ const struct riscv_opcode riscv_opcodes[] =
  74. {"vmand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
  75. {"vmnand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
  76. -{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNOTMM, MASK_VMANDNOTMM, match_opcode, 0},
  77. +{"vmandn.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, 0},
  78. +{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, INSN_ALIAS},
  79. {"vmxor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
  80. {"vmor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
  81. {"vmnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
  82. -{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNOTMM, MASK_VMORNOTMM, match_opcode, 0},
  83. +{"vmorn.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, 0},
  84. +{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, INSN_ALIAS},
  85. {"vmxnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
  86. -{"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
  87. +{"vcpop.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VCPOPM, MASK_VCPOPM, match_opcode, 0},
  88. +{"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VCPOPM, MASK_VCPOPM, match_opcode, INSN_ALIAS},
  89. {"vfirst.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
  90. {"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0},
  91. {"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0},
  92. --
  93. 2.25.1