0010-Add-support-for-Netlogic-XLP.patch 19 KB

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  1. From 21920b7a3d10a7dae4c1f18a4bb185de78048e3f Mon Sep 17 00:00:00 2001
  2. From: Khem Raj <raj.khem@gmail.com>
  3. Date: Sun, 14 Feb 2016 17:06:19 +0000
  4. Subject: [PATCH] Add support for Netlogic XLP
  5. Patch From: Nebu Philips <nphilips@netlogicmicro.com>
  6. Using the mipsisa64r2nlm target, add support for XLP from
  7. Netlogic. Also, update vendor name to NLM wherever applicable.
  8. Use 0x00000080 for INSN_XLP, the value 0x00000040 has already been
  9. assigned to INSN_OCTEON3
  10. Upstream-Status: Pending
  11. Signed-off-by: Khem Raj <raj.khem@gmail.com>
  12. Signed-off-by: Baoshan Pang <baoshan.pang@windriver.com>
  13. Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
  14. ---
  15. bfd/aoutx.h | 1 +
  16. bfd/archures.c | 1 +
  17. bfd/bfd-in2.h | 1 +
  18. bfd/config.bfd | 5 +++++
  19. bfd/cpu-mips.c | 6 ++++--
  20. bfd/elfxx-mips.c | 8 ++++++++
  21. binutils/readelf.c | 1 +
  22. gas/config/tc-mips.c | 4 +++-
  23. gas/configure | 3 +++
  24. gas/configure.ac | 3 +++
  25. include/elf/mips.h | 1 +
  26. include/opcode/mips.h | 8 +++++++-
  27. ld/configure.tgt | 3 +++
  28. opcodes/mips-dis.c | 12 +++++-------
  29. opcodes/mips-opc.c | 31 ++++++++++++++++++++-----------
  30. 15 files changed, 66 insertions(+), 22 deletions(-)
  31. diff --git a/bfd/aoutx.h b/bfd/aoutx.h
  32. index 17560bd8f54..10b1cad74e6 100644
  33. --- a/bfd/aoutx.h
  34. +++ b/bfd/aoutx.h
  35. @@ -810,6 +810,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
  36. case bfd_mach_mipsisa64r6:
  37. case bfd_mach_mips_sb1:
  38. case bfd_mach_mips_xlr:
  39. + case bfd_mach_mips_xlp:
  40. /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
  41. arch_flags = M_MIPS2;
  42. break;
  43. diff --git a/bfd/archures.c b/bfd/archures.c
  44. index 390691bfba1..b0b7a5fa7a0 100644
  45. --- a/bfd/archures.c
  46. +++ b/bfd/archures.c
  47. @@ -185,6 +185,7 @@ DESCRIPTION
  48. .#define bfd_mach_mips_octeon3 6503
  49. .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR'. *}
  50. .#define bfd_mach_mips_interaptiv_mr2 736550 {* decimal 'IA2'. *}
  51. +.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP'. *}
  52. .#define bfd_mach_mipsisa32 32
  53. .#define bfd_mach_mipsisa32r2 33
  54. .#define bfd_mach_mipsisa32r3 34
  55. diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
  56. index 57b3c453649..a00b0d44359 100644
  57. --- a/bfd/bfd-in2.h
  58. +++ b/bfd/bfd-in2.h
  59. @@ -1562,6 +1562,7 @@ enum bfd_architecture
  60. #define bfd_mach_mips_octeon3 6503
  61. #define bfd_mach_mips_xlr 887682 /* decimal 'XLR'. */
  62. #define bfd_mach_mips_interaptiv_mr2 736550 /* decimal 'IA2'. */
  63. +#define bfd_mach_mips_xlp 887680 /* decimal 'XLP'. */
  64. #define bfd_mach_mipsisa32 32
  65. #define bfd_mach_mipsisa32r2 33
  66. #define bfd_mach_mipsisa32r3 34
  67. diff --git a/bfd/config.bfd b/bfd/config.bfd
  68. index 1896e11790c..8270fd2708d 100644
  69. --- a/bfd/config.bfd
  70. +++ b/bfd/config.bfd
  71. @@ -874,6 +874,11 @@ case "${targ}" in
  72. targ_defvec=mips_elf32_le_vec
  73. targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec"
  74. ;;
  75. + mipsisa64*-*-elf*)
  76. + targ_defvec=mips_elf32_trad_be_vec
  77. + targ_selvecs="mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec"
  78. + want64=true
  79. + ;;
  80. mips*-*-elf* | mips*-*-rtems* | mips*-*-windiss | mips*-*-none)
  81. targ_defvec=mips_elf32_be_vec
  82. targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec"
  83. diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
  84. index 76b507e3c77..c1563cf4319 100644
  85. --- a/bfd/cpu-mips.c
  86. +++ b/bfd/cpu-mips.c
  87. @@ -108,7 +108,8 @@ enum
  88. I_mipsocteon3,
  89. I_xlr,
  90. I_interaptiv_mr2,
  91. - I_micromips
  92. + I_micromips,
  93. + I_xlp
  94. };
  95. #define NN(index) (&arch_info_struct[(index) + 1])
  96. @@ -163,7 +164,8 @@ static const bfd_arch_info_type arch_info_struct[] =
  97. N (64, 64, bfd_mach_mips_xlr, "mips:xlr", false, NN(I_xlr)),
  98. N (32, 32, bfd_mach_mips_interaptiv_mr2, "mips:interaptiv-mr2", false,
  99. NN(I_interaptiv_mr2)),
  100. - N (64, 64, bfd_mach_mips_micromips, "mips:micromips", false, NULL)
  101. + N (64, 64, bfd_mach_mips_micromips, "mips:micromips", false, NN(I_micromips)),
  102. + N (64, 64, bfd_mach_mips_xlp, "mips:xlp", false, NULL)
  103. };
  104. /* The default architecture is mips:3000, but with a machine number of
  105. diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
  106. index e4827fd17de..fa8c2512837 100644
  107. --- a/bfd/elfxx-mips.c
  108. +++ b/bfd/elfxx-mips.c
  109. @@ -6980,6 +6980,9 @@ _bfd_elf_mips_mach (flagword flags)
  110. case E_MIPS_MACH_IAMR2:
  111. return bfd_mach_mips_interaptiv_mr2;
  112. + case E_MIPS_MACH_XLP:
  113. + return bfd_mach_mips_xlp;
  114. +
  115. default:
  116. switch (flags & EF_MIPS_ARCH)
  117. {
  118. @@ -12339,6 +12342,10 @@ mips_set_isa_flags (bfd *abfd)
  119. val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
  120. break;
  121. + case bfd_mach_mips_xlp:
  122. + val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_XLP;
  123. + break;
  124. +
  125. case bfd_mach_mipsisa32:
  126. val = E_MIPS_ARCH_32;
  127. break;
  128. @@ -14428,6 +14435,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
  129. { bfd_mach_mips_gs264e, bfd_mach_mips_gs464e },
  130. { bfd_mach_mips_gs464e, bfd_mach_mips_gs464 },
  131. { bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
  132. + { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 },
  133. /* MIPS64 extensions. */
  134. { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
  135. diff --git a/binutils/readelf.c b/binutils/readelf.c
  136. index a6073f7ec80..2f2448b5eba 100644
  137. --- a/binutils/readelf.c
  138. +++ b/binutils/readelf.c
  139. @@ -3613,6 +3613,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
  140. case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
  141. case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
  142. case E_MIPS_MACH_IAMR2: strcat (buf, ", interaptiv-mr2"); break;
  143. + case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break;
  144. case 0:
  145. /* We simply ignore the field in this case to avoid confusion:
  146. MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
  147. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
  148. index 0201f816814..a3cfcdbe982 100644
  149. --- a/gas/config/tc-mips.c
  150. +++ b/gas/config/tc-mips.c
  151. @@ -570,6 +570,7 @@ static int mips_32bitmode = 0;
  152. || mips_opts.arch == CPU_RM7000 \
  153. || mips_opts.arch == CPU_VR5500 \
  154. || mips_opts.micromips \
  155. + || mips_opts.arch == CPU_XLP \
  156. )
  157. /* Whether the processor uses hardware interlocks to protect reads
  158. @@ -599,6 +600,7 @@ static int mips_32bitmode = 0;
  159. && mips_opts.isa != ISA_MIPS3) \
  160. || mips_opts.arch == CPU_R4300 \
  161. || mips_opts.micromips \
  162. + || mips_opts.arch == CPU_XLP \
  163. )
  164. /* Whether the processor uses hardware interlocks to protect reads
  165. @@ -20157,7 +20159,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
  166. /* Broadcom XLP.
  167. XLP is mostly like XLR, with the prominent exception that it is
  168. MIPS64R2 rather than MIPS64. */
  169. - { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
  170. + { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP },
  171. /* MIPS 64 Release 6. */
  172. { "i6400", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
  173. diff --git a/gas/configure b/gas/configure
  174. index 110d707f079..789d1b38b33 100755
  175. --- a/gas/configure
  176. +++ b/gas/configure
  177. @@ -12083,6 +12083,9 @@ _ACEOF
  178. mipsisa64r6 | mipsisa64r6el)
  179. mips_cpu=mips64r6
  180. ;;
  181. + mipsisa64r2nlm | mipsisa64r2nlmel)
  182. + mips_cpu=xlp
  183. + ;;
  184. mipstx39 | mipstx39el)
  185. mips_cpu=r3900
  186. ;;
  187. diff --git a/gas/configure.ac b/gas/configure.ac
  188. index 78efba88e23..c1b4ef6b3b0 100644
  189. --- a/gas/configure.ac
  190. +++ b/gas/configure.ac
  191. @@ -331,6 +331,9 @@ changequote([,])dnl
  192. mipsisa64r6 | mipsisa64r6el)
  193. mips_cpu=mips64r6
  194. ;;
  195. + mipsisa64r2nlm | mipsisa64r2nlmel)
  196. + mips_cpu=xlp
  197. + ;;
  198. mipstx39 | mipstx39el)
  199. mips_cpu=r3900
  200. ;;
  201. diff --git a/include/elf/mips.h b/include/elf/mips.h
  202. index 4bd86307120..2d7df22abf2 100644
  203. --- a/include/elf/mips.h
  204. +++ b/include/elf/mips.h
  205. @@ -290,6 +290,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
  206. #define E_MIPS_MACH_SB1 0x008a0000
  207. #define E_MIPS_MACH_OCTEON 0x008b0000
  208. #define E_MIPS_MACH_XLR 0x008c0000
  209. +#define E_MIPS_MACH_XLP 0x008f0000
  210. #define E_MIPS_MACH_OCTEON2 0x008d0000
  211. #define E_MIPS_MACH_OCTEON3 0x008e0000
  212. #define E_MIPS_MACH_5400 0x00910000
  213. diff --git a/include/opcode/mips.h b/include/opcode/mips.h
  214. index 9add3c9d5bf..a99c53f652f 100644
  215. --- a/include/opcode/mips.h
  216. +++ b/include/opcode/mips.h
  217. @@ -1157,7 +1157,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
  218. #define INSN_ISA32R3 8
  219. #define INSN_ISA32R5 9
  220. #define INSN_ISA32R6 10
  221. -#define INSN_ISA64 11
  222. +#define INSN_ISA64 11
  223. #define INSN_ISA64R2 12
  224. #define INSN_ISA64R3 13
  225. #define INSN_ISA64R5 14
  226. @@ -1265,6 +1265,8 @@ static const unsigned int mips_isa_table[] = {
  227. #define INSN_XLR 0x00000020
  228. /* Imagination interAptiv MR2. */
  229. #define INSN_INTERAPTIV_MR2 0x04000000
  230. +/* Netlogic XlP instruction */
  231. +#define INSN_XLP 0x00000080
  232. /* DSP ASE */
  233. #define ASE_DSP 0x00000001
  234. @@ -1389,6 +1391,7 @@ static const unsigned int mips_isa_table[] = {
  235. #define CPU_OCTEON3 6503
  236. #define CPU_XLR 887682 /* decimal 'XLR' */
  237. #define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */
  238. +#define CPU_XLP 887680 /* decimal 'XLP' */
  239. /* Return true if the given CPU is included in INSN_* mask MASK. */
  240. @@ -1459,6 +1462,9 @@ cpu_is_member (int cpu, unsigned int mask)
  241. case CPU_INTERAPTIV_MR2:
  242. return (mask & INSN_INTERAPTIV_MR2) != 0;
  243. + case CPU_XLP:
  244. + return (mask & INSN_XLP) != 0;
  245. +
  246. default:
  247. return false;
  248. }
  249. diff --git a/ld/configure.tgt b/ld/configure.tgt
  250. index c08533658e5..7abf32215c2 100644
  251. --- a/ld/configure.tgt
  252. +++ b/ld/configure.tgt
  253. @@ -509,6 +509,9 @@ mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
  254. targ_emul=elf32btsmip
  255. targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip"
  256. ;;
  257. +mipsisa64*-*-elf*) targ_emul=elf32btsmip
  258. + targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip"
  259. + ;;
  260. mips64*el-ps2-elf*) targ_emul=elf32lr5900n32
  261. targ_extra_emuls="elf32lr5900"
  262. targ_extra_libpath=$targ_extra_emuls
  263. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
  264. index 591caf11e28..00120afed47 100644
  265. --- a/opcodes/mips-dis.c
  266. +++ b/opcodes/mips-dis.c
  267. @@ -698,13 +698,11 @@ const struct mips_arch_choice mips_arch_choices[] =
  268. mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
  269. mips_cp1_names_mips3264, mips_hwr_names_numeric },
  270. - /* XLP is mostly like XLR, with the prominent exception it is being
  271. - MIPS64R2. */
  272. - { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
  273. - ISA_MIPS64R2 | INSN_XLR, 0,
  274. - mips_cp0_names_xlr,
  275. - mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
  276. - mips_cp1_names_mips3264, mips_hwr_names_numeric },
  277. + { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP,
  278. + ISA_MIPS64R2 | INSN_XLP, 0,
  279. + mips_cp0_names_mips3264r2,
  280. + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
  281. + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
  282. /* This entry, mips16, is here only for ISA/processor selection; do
  283. not print its name. */
  284. diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
  285. index db72c039bfd..ff2fa614de1 100644
  286. --- a/opcodes/mips-opc.c
  287. +++ b/opcodes/mips-opc.c
  288. @@ -329,6 +329,7 @@ decode_mips_operand (const char *p)
  289. #define IOCT3 INSN_OCTEON3
  290. #define XLR INSN_XLR
  291. #define IAMR2 INSN_INTERAPTIV_MR2
  292. +#define XLP INSN_XLP
  293. #define IVIRT ASE_VIRT
  294. #define IVIRT64 ASE_VIRT64
  295. @@ -991,6 +992,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  296. {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
  297. {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 },
  298. {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
  299. +{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
  300. /* ctc0 is at the bottom of the table. */
  301. {"ctc1", "t,g", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
  302. {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
  303. @@ -1023,12 +1025,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
  304. {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
  305. {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
  306. {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
  307. -{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 },
  308. +{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR|XLP, 0, 0 },
  309. {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 },
  310. {"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
  311. {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
  312. {"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
  313. {"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
  314. +{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
  315. /* dctr and dctw are used on the r5000. */
  316. {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
  317. {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
  318. @@ -1100,6 +1103,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  319. {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 },
  320. {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
  321. {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
  322. +{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_1, 0, XLP, 0, 0 },
  323. {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
  324. {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
  325. {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE },
  326. @@ -1113,6 +1117,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
  327. /* dmfc2 is at the bottom of the table. */
  328. /* dmtc2 is at the bottom of the table. */
  329. {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
  330. +{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_1, 0, XLP, 0, 0 },
  331. +{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
  332. {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
  333. {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 },
  334. {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 },
  335. @@ -1266,9 +1272,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
  336. {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 },
  337. {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 },
  338. {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 },
  339. -{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
  340. -{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
  341. -{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
  342. +{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
  343. +{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
  344. +{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
  345. {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
  346. {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
  347. {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
  348. @@ -1437,7 +1443,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  349. {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 },
  350. {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 },
  351. {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 },
  352. -{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 },
  353. +{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR|XLP, 0, 0 },
  354. {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 },
  355. {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
  356. {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
  357. @@ -1482,10 +1488,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
  358. /* move is at the top of the table. */
  359. {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
  360. {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 },
  361. +{"msgsnds", "d,t", 0x4a000001, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
  362. {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 },
  363. {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 },
  364. -{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 },
  365. -{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 },
  366. +{"msglds", "d,t", 0x4a000002, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
  367. +{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP, 0, 0 },
  368. +{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP, 0, 0 },
  369. +{"msgsync", "", 0x4a000004, 0xffffffff,0, 0, XLP, 0, 0 },
  370. {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 },
  371. {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  372. {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 },
  373. @@ -1535,7 +1544,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  374. {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 },
  375. {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 },
  376. {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
  377. -{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 },
  378. +{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 },
  379. {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
  380. {"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
  381. {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
  382. @@ -1977,9 +1986,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
  383. {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37},
  384. {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
  385. {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 },
  386. -{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
  387. -{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
  388. -{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
  389. +{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
  390. +{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
  391. +{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
  392. {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, I2 },
  393. {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, I2 },
  394. {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },