123456789101112131415161718192021222324252627282930313233 |
- From 8c1459b734f8cfe1562d72ad302d3dfa55fa85e7 Mon Sep 17 00:00:00 2001
- From: "max.ma" <max.ma@starfivetech.com>
- Date: Mon, 28 Feb 2022 18:49:58 -0800
- Subject: [PATCH 06/19] change memcpy_vector LMUL to m8
- ---
- sysdeps/riscv/rv64/multiarch/memcpy_vector.S | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
- diff --git a/sysdeps/riscv/rv64/multiarch/memcpy_vector.S b/sysdeps/riscv/rv64/multiarch/memcpy_vector.S
- index 2319647de8..bae330f6e0 100644
- --- a/sysdeps/riscv/rv64/multiarch/memcpy_vector.S
- +++ b/sysdeps/riscv/rv64/multiarch/memcpy_vector.S
- @@ -34,14 +34,14 @@ ENTRY (memcpy)
- li a6, 16
- beqz a5, .loop_cpy
- sub a5, a6, a5
- - vsetvli t0, a5, e8, m4
- + vsetvli t0, a5, e8, m8
- vle8.v v0, (a1)
- add a1, a1, t0
- sub a2, a2, t0
- vse8.v v0, (a3)
- add a3, a3, t0
- .loop_cpy:
- - vsetvli t0, a2, e8, m4
- + vsetvli t0, a2, e8, m8
- vle8.v v0, (a1)
- add a1, a1, t0
- sub a2, a2, t0
- --
- 2.25.1
|