0004-add-pref-instruction.patch 2.9 KB

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  1. From e4acc8143a553e7dbd039e76d42ee74e568546ae Mon Sep 17 00:00:00 2001
  2. From: "max.ma" <max.ma@starfivetech.com>
  3. Date: Sun, 20 Mar 2022 22:12:45 -0700
  4. Subject: [PATCH 4/5] add pref instruction
  5. ---
  6. gas/config/tc-riscv.c | 24 ++++++++++++------------
  7. opcodes/riscv-opc.c | 1 +
  8. 2 files changed, 13 insertions(+), 12 deletions(-)
  9. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  10. index cae279b647..672de3e33a 100644
  11. --- a/gas/config/tc-riscv.c
  12. +++ b/gas/config/tc-riscv.c
  13. @@ -1380,7 +1380,7 @@ check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
  14. static bfd_boolean check_pref_type(unsigned long type)
  15. {
  16. - if (type != 0 && type != 1 && type != 3 && type != 8)
  17. + if (type != 0 && type != 1 && type != 2 && type != 3 && type != 8)
  18. as_bad (_("Improper pref type (%lu)"), type);
  19. }
  20. @@ -2471,20 +2471,20 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
  21. s = expr_end;
  22. continue;
  23. - case '#':
  24. - my_getExpression (imm_expr, s);
  25. - check_pref_type((unsigned long)imm_expr->X_add_number);
  26. - INSERT_OPERAND (PREF_TYPE, *ip, imm_expr->X_add_number);
  27. - imm_expr->X_op = O_absent;
  28. - s = expr_end;
  29. - continue;
  30. + case '#':
  31. + my_getExpression (imm_expr, s);
  32. + check_pref_type((unsigned long)imm_expr->X_add_number);
  33. + INSERT_OPERAND (PREF_TYPE, *ip, imm_expr->X_add_number);
  34. + imm_expr->X_op = O_absent;
  35. + s = expr_end;
  36. + continue;
  37. - case '+':
  38. + case '+':
  39. my_getExpression (imm_expr, s);
  40. check_absolute_expr (ip, imm_expr, FALSE);
  41. - if ((unsigned long) imm_expr->X_add_number > 0xff)
  42. - as_bad (_("Improper pref offset value (%lu)"),
  43. - (unsigned long) imm_expr->X_add_number);
  44. + if (imm_expr->X_add_number > 127 || imm_expr->X_add_number < -128)
  45. + as_bad (_("Improper pref offset value (%d)"),
  46. + (long) imm_expr->X_add_number);
  47. INSERT_OPERAND (PREF_OFFSET, *ip, imm_expr->X_add_number);
  48. imm_expr->X_op = O_absent;
  49. s = expr_end;
  50. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  51. index a7c697a938..1fd2fc4a9f 100644
  52. --- a/opcodes/riscv-opc.c
  53. +++ b/opcodes/riscv-opc.c
  54. @@ -758,6 +758,7 @@ const struct riscv_opcode riscv_opcodes[] =
  55. {"snez", 0, INSN_CLASS_I, "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS },
  56. {"sltz", 0, INSN_CLASS_I, "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS },
  57. {"sgtz", 0, INSN_CLASS_I, "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS },
  58. +{"pref", 0, INSN_CLASS_I, "#,+(s)", MATCH_SLTI, MASK_PREF, match_opcode, INSN_ALIAS },
  59. {"slti", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
  60. {"slt", 0, INSN_CLASS_I, "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 },
  61. {"slt", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
  62. --
  63. 2.25.1