0003-RISC-V-Hypervisor-ext-support-Privileged-Spec-1.12.patch 12 KB

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  1. From 20fe3cece92e9a3b53b09970fe18857ae95a7ca0 Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Mon, 17 Jan 2022 18:02:26 +0800
  4. Subject: [PATCH 3/3] RISC-V: Hypervisor ext: support Privileged Spec 1.12
  5. - Hypervisor Memory-Management Instructions
  6. HFENCE.VVMA, HFENCE.GVMA,
  7. - Hypervisor Virtual Machine Load and Store Instructions
  8. HLV.B, HLV.BU, HSV.B,
  9. HLV.H, HLV.HU, HLVX.HU, HSB.H,
  10. HLV.W, HLV.WU, HLVX.WU, HSV.W,
  11. HLV.D, HSV.D
  12. - Hypervisor CSRs (some new, some address changed)
  13. hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip,
  14. htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah,
  15. vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp
  16. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  17. ---
  18. bfd/cpu-riscv.c | 1 +
  19. gas/config/tc-riscv.c | 3 ++
  20. include/opcode/riscv-opc.h | 95 +++++++++++++++++++++++++++++++++++++-
  21. include/opcode/riscv.h | 2 +
  22. opcodes/riscv-opc.c | 23 +++++++++
  23. 5 files changed, 123 insertions(+), 1 deletion(-)
  24. diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c
  25. index 2e9e9eb9d2..b7d7e11c70 100644
  26. --- a/bfd/cpu-riscv.c
  27. +++ b/bfd/cpu-riscv.c
  28. @@ -40,6 +40,7 @@ static const struct priv_spec_t priv_specs[] =
  29. {"1.9.1", PRIV_SPEC_CLASS_1P9P1},
  30. {"1.10", PRIV_SPEC_CLASS_1P10},
  31. {"1.11", PRIV_SPEC_CLASS_1P11},
  32. + {"1.12", PRIV_SPEC_CLASS_1P12},
  33. /* Terminate the list. */
  34. {NULL, 0}
  35. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  36. index e1bf3992a6..cae279b647 100644
  37. --- a/gas/config/tc-riscv.c
  38. +++ b/gas/config/tc-riscv.c
  39. @@ -254,6 +254,9 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
  40. || riscv_subset_supports ("zvamo")));
  41. case INSN_CLASS_V_OR_ZVLSSEG:
  42. return riscv_subset_supports ("v") || riscv_subset_supports ("zvlsseg");
  43. + case INSN_CLASS_H:
  44. + return riscv_subset_supports ("i");
  45. +
  46. default:
  47. as_fatal ("Unreachable");
  48. return FALSE;
  49. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  50. index eea10e1ebc..b919720d75 100644
  51. --- a/include/opcode/riscv-opc.h
  52. +++ b/include/opcode/riscv-opc.h
  53. @@ -2612,6 +2612,27 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
  54. #define MATCH_VFDOTVV 0xe4001057
  55. #define MASK_VFDOTVV 0xfc00707f
  56. /* END RVV */
  57. +#define MASK_HLV 0xfff0707f
  58. +#define MATCH_HLVB 0x60004073
  59. +#define MATCH_HLVBU 0x60104073
  60. +#define MATCH_HLVH 0x64004073
  61. +#define MATCH_HLVHU 0x64104073
  62. +#define MATCH_HLVXHU 0x64304073
  63. +#define MATCH_HLVW 0x68004073
  64. +#define MATCH_HLVXWU 0x68304073
  65. +#define MATCH_HLVWU 0x68104073
  66. +#define MATCH_HLVD 0x6c004073
  67. +
  68. +#define MASK_HSV 0xfe007fff
  69. +#define MATCH_HSVB 0x62004073
  70. +#define MATCH_HSVH 0x66004073
  71. +#define MATCH_HSVW 0x6a004073
  72. +#define MATCH_HSVD 0x6e004073
  73. +
  74. +#define MASK_HFENCE_VVMA 0xfe007fff
  75. +#define MATCH_HFENCE_VVMA 0x22000073
  76. +#define MASK_HFENCE_GVMA 0xfe007fff
  77. +#define MATCH_HFENCE_GVMA 0x62000073
  78. #define MATCH_CUSTOM0 0xb
  79. #define MASK_CUSTOM0 0x707f
  80. @@ -2874,6 +2895,33 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
  81. #define CSR_MHPMEVENT29 0x33d
  82. #define CSR_MHPMEVENT30 0x33e
  83. #define CSR_MHPMEVENT31 0x33f
  84. +/* Hypervisor Extension v1.0 (Privileged spec 1.12). */
  85. +#define CSR_HSTATUS 0x600
  86. +#define CSR_HEDELEG 0x602
  87. +#define CSR_HIDELEG 0x603
  88. +#define CSR_HIE 0x604
  89. +#define CSR_HCOUNTEREN 0x606
  90. +#define CSR_HGEIE 0x607
  91. +#define CSR_HTVAL 0x643
  92. +#define CSR_HIP 0x644
  93. +#define CSR_HVIP 0x645
  94. +#define CSR_HTINST 0x64a
  95. +#define CSR_HGEIP 0xe12
  96. +#define CSR_HENVCFG 0x60a
  97. +#define CSR_HENVCFGH 0x61a
  98. +#define CSR_HGATP 0x680
  99. +#define CSR_HCONTEXT 0x6a8
  100. +#define CSR_HTIMEDELTA 0x605
  101. +#define CSR_HTIMEDELTAH 0x615
  102. +#define CSR_VSSTATUS 0x200
  103. +#define CSR_VSIE 0x204
  104. +#define CSR_VSTVEC 0x205
  105. +#define CSR_VSSCRATCH 0x240
  106. +#define CSR_VSEPC 0x241
  107. +#define CSR_VSCAUSE 0x242
  108. +#define CSR_VSTVAL 0x243
  109. +#define CSR_VSIP 0x244
  110. +#define CSR_VSATP 0x280
  111. #define CSR_MBASE 0x380
  112. #define CSR_MBOUND 0x381
  113. #define CSR_MIBASE 0x382
  114. @@ -3023,6 +3071,22 @@ DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
  115. DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
  116. DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
  117. DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
  118. +DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA)
  119. +DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA)
  120. +DECLARE_INSN(hlv_b, MATCH_HLVB, MASK_HLV)
  121. +DECLARE_INSN(hlv_h, MATCH_HLVH, MASK_HLV)
  122. +DECLARE_INSN(hlv_w, MATCH_HLVW, MASK_HLV)
  123. +DECLARE_INSN(hlv_d, MATCH_HLVD, MASK_HLV)
  124. +DECLARE_INSN(hlv_bu, MATCH_HLVBU, MASK_HLV)
  125. +DECLARE_INSN(hlv_hu, MATCH_HLVHU, MASK_HLV)
  126. +DECLARE_INSN(hlv_wu, MATCH_HLVWU, MASK_HLV)
  127. +DECLARE_INSN(hlvx_hu, MATCH_HLVXHU, MASK_HLV)
  128. +DECLARE_INSN(hlvx_wu, MATCH_HLVXWU, MASK_HLV)
  129. +DECLARE_INSN(hsv_b, MATCH_HSVB, MASK_HSV)
  130. +DECLARE_INSN(hsv_h, MATCH_HSVH, MASK_HSV)
  131. +DECLARE_INSN(hsv_w, MATCH_HSVW, MASK_HSV)
  132. +DECLARE_INSN(hsv_d, MATCH_HSVD, MASK_HSV)
  133. +
  134. /* Custom CSRs instruction */
  135. DECLARE_INSN(cflush_d_l1, MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1)
  136. DECLARE_INSN(cdiscard_d_l1, MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1)
  137. @@ -3515,6 +3579,35 @@ DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR
  138. DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
  139. DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
  140. DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
  141. +/* Hypervisor Ext v1.0 (Privileged spec 1.12). */
  142. +/* TODO: Fix to CSR_CLASS_H when explicit h-ext arch string is introduced. */
  143. +DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  144. +DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  145. +DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  146. +DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  147. +DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  148. +DECLARE_CSR(hgeie, CSR_HGEIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  149. +DECLARE_CSR(htval, CSR_HTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  150. +DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  151. +DECLARE_CSR(hvip, CSR_HVIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  152. +DECLARE_CSR(htinst, CSR_HTINST, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  153. +DECLARE_CSR(hgeip, CSR_HGEIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  154. +DECLARE_CSR(henvcfg, CSR_HENVCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  155. +DECLARE_CSR(henvcfgh, CSR_HENVCFGH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  156. +DECLARE_CSR(hgatp, CSR_HGATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  157. +DECLARE_CSR(hcontext, CSR_HCONTEXT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  158. +DECLARE_CSR(htimedelta, CSR_HTIMEDELTA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  159. +DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  160. +DECLARE_CSR(vsstatus, CSR_VSSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  161. +DECLARE_CSR(vsie, CSR_VSIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  162. +DECLARE_CSR(vstvec, CSR_VSTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  163. +DECLARE_CSR(vsscratch, CSR_VSSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  164. +DECLARE_CSR(vsepc, CSR_VSEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  165. +DECLARE_CSR(vscause, CSR_VSCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  166. +DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  167. +DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  168. +DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  169. +
  170. /* Dropped. */
  171. DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  172. DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  173. @@ -3561,4 +3654,4 @@ DECLARE_CSR_ALIAS(itrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, P
  174. DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  175. DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  176. DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  177. -#endif /* DECLARE_CSR_ALIAS. */
  178. \ No newline at end of file
  179. +#endif /* DECLARE_CSR_ALIAS. */
  180. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
  181. index ee0d277031..ac48eca67d 100644
  182. --- a/include/opcode/riscv.h
  183. +++ b/include/opcode/riscv.h
  184. @@ -398,6 +398,7 @@ enum riscv_insn_class
  185. INSN_CLASS_V_AND_F,
  186. INSN_CLASS_V_OR_ZVAMO,
  187. INSN_CLASS_V_OR_ZVLSSEG,
  188. + INSN_CLASS_H,
  189. };
  190. /* This structure holds information for a particular instruction. */
  191. @@ -476,6 +477,7 @@ enum riscv_priv_spec_class
  192. PRIV_SPEC_CLASS_1P9P1,
  193. PRIV_SPEC_CLASS_1P10,
  194. PRIV_SPEC_CLASS_1P11,
  195. + PRIV_SPEC_CLASS_1P12,
  196. PRIV_SPEC_CLASS_DRAFT
  197. };
  198. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  199. index ffa817cc65..a7c697a938 100644
  200. --- a/opcodes/riscv-opc.c
  201. +++ b/opcodes/riscv-opc.c
  202. @@ -2209,6 +2209,29 @@ const struct riscv_opcode riscv_insn_types[] =
  203. {"cb", 0, INSN_CLASS_F_AND_C, "O2,CF3,CS,Cp", 0, 0, match_opcode, 0 },
  204. {"cj", 0, INSN_CLASS_C, "O2,CF3,Ca", 0, 0, match_opcode, 0 },
  205. +
  206. +/* Svinval instructions + Hypervisor Ext v1.0. */
  207. +{"hfence.vvma", 0, INSN_CLASS_H, "s,t", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA, match_opcode, 0 },
  208. +{"hfence.gvma", 0, INSN_CLASS_H, "", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS1|MASK_RS2, match_opcode, 0 },
  209. +{"hfence.gvma", 0, INSN_CLASS_H, "s", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS2, match_opcode, 0 },
  210. +{"hfence.gvma", 0, INSN_CLASS_H, "s,t", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA, match_opcode, 0 },
  211. +
  212. +/* Hypervisor Ext v1.0 (Privileged spec 1.12). */
  213. +{"hlv.b", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVB, MASK_HLV, match_opcode, INSN_DREF|INSN_1_BYTE },
  214. +{"hlv.bu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVBU, MASK_HLV, match_opcode, INSN_DREF|INSN_1_BYTE },
  215. +{"hlv.h", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVH, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE },
  216. +{"hlv.hu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVHU, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE },
  217. +{"hlvx.hu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVXHU, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE },
  218. +{"hlv.w", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVW, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE },
  219. +{"hlv.wu", 64, INSN_CLASS_H, "d,0(s)", MATCH_HLVWU, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE },
  220. +{"hlvx.wu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVXWU, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE },
  221. +{"hlv.d", 64, INSN_CLASS_H, "d,0(s)", MATCH_HLVD, MASK_HLV, match_opcode, INSN_DREF|INSN_8_BYTE },
  222. +
  223. +{"hsv.b", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVB, MASK_HSV, match_opcode, INSN_DREF|INSN_1_BYTE },
  224. +{"hsv.h", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVH, MASK_HSV, match_opcode, INSN_DREF|INSN_2_BYTE },
  225. +{"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVW, MASK_HSV, match_opcode, INSN_DREF|INSN_4_BYTE },
  226. +{"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSVD, MASK_HSV, match_opcode, INSN_DREF|INSN_8_BYTE },
  227. +
  228. /* Terminate the list. */
  229. {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
  230. };
  231. --
  232. 2.33.1