0002-RISC-V-Hypervisor-ext-drop-Privileged-Spec-1.9.1-and.patch 14 KB

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  1. From 3421d7e55585065cc08ac9a142dc6fa66a42c173 Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Mon, 17 Jan 2022 14:38:48 +0800
  4. Subject: [PATCH 2/3] RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 and
  5. fixed compiled error bug
  6. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  7. ---
  8. gas/config/tc-riscv.c | 4 ++--
  9. gas/testsuite/gas/riscv/csr-dw-regnums.d | 10 ----------
  10. gas/testsuite/gas/riscv/csr-dw-regnums.s | 10 ----------
  11. .../gas/riscv/priv-reg-fail-version-1p10.l | 10 ----------
  12. .../gas/riscv/priv-reg-fail-version-1p11.l | 10 ----------
  13. .../gas/riscv/priv-reg-version-1p10.d | 10 ----------
  14. .../gas/riscv/priv-reg-version-1p11.d | 10 ----------
  15. gas/testsuite/gas/riscv/priv-reg.s | 10 ----------
  16. include/opcode/riscv-opc.h | 20 -------------------
  17. include/opcode/riscv.h | 13 ++++++++++++
  18. 10 files changed, 15 insertions(+), 92 deletions(-)
  19. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  20. index 45f5bda4a2..e1bf3992a6 100644
  21. --- a/gas/config/tc-riscv.c
  22. +++ b/gas/config/tc-riscv.c
  23. @@ -725,7 +725,7 @@ riscv_csr_address (const char *csr_name,
  24. result = (riscv_subset_supports ("v")
  25. || riscv_subset_supports ("zvamo")
  26. || riscv_subset_supports ("zvlsseg"));
  27. - need_check_version = false;
  28. + need_check_version = FALSE;
  29. break;
  30. default:
  31. as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
  32. @@ -1573,7 +1573,7 @@ vector_macro (struct riscv_cl_insn *ip)
  33. /* Zero extend and sign extend byte/half-word/word. */
  34. static void
  35. -riscv_ext (int destreg, int srcreg, unsigned shift, bool sign)
  36. +riscv_ext (int destreg, int srcreg, unsigned shift, _Bool sign)
  37. {
  38. if (sign)
  39. {
  40. diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
  41. index de17ad81fb..ea0a445c39 100644
  42. --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
  43. +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
  44. @@ -229,16 +229,6 @@ Contents of the .* section:
  45. DW_CFA_offset_extended_sf: r4925 \(mhpmevent29\) at cfa\+3316
  46. DW_CFA_offset_extended_sf: r4926 \(mhpmevent30\) at cfa\+3320
  47. DW_CFA_offset_extended_sf: r4927 \(mhpmevent31\) at cfa\+3324
  48. - DW_CFA_offset_extended_sf: r4608 \(hstatus\) at cfa\+2048
  49. - DW_CFA_offset_extended_sf: r4610 \(hedeleg\) at cfa\+2056
  50. - DW_CFA_offset_extended_sf: r4611 \(hideleg\) at cfa\+2060
  51. - DW_CFA_offset_extended_sf: r4612 \(hie\) at cfa\+2064
  52. - DW_CFA_offset_extended_sf: r4613 \(htvec\) at cfa\+2068
  53. - DW_CFA_offset_extended_sf: r4672 \(hscratch\) at cfa\+2304
  54. - DW_CFA_offset_extended_sf: r4673 \(hepc\) at cfa\+2308
  55. - DW_CFA_offset_extended_sf: r4674 \(hcause\) at cfa\+2312
  56. - DW_CFA_offset_extended_sf: r4675 \(hbadaddr\) at cfa\+2316
  57. - DW_CFA_offset_extended_sf: r4676 \(hip\) at cfa\+2320
  58. DW_CFA_offset_extended_sf: r4992 \(mbase\) at cfa\+3584
  59. DW_CFA_offset_extended_sf: r4993 \(mbound\) at cfa\+3588
  60. DW_CFA_offset_extended_sf: r4994 \(mibase\) at cfa\+3592
  61. diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
  62. index ecc8014697..549475d650 100644
  63. --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
  64. +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
  65. @@ -220,16 +220,6 @@ _start:
  66. .cfi_offset mhpmevent30, 3320
  67. .cfi_offset mhpmevent31, 3324
  68. # dropped
  69. - .cfi_offset hstatus, 2048
  70. - .cfi_offset hedeleg, 2056
  71. - .cfi_offset hideleg, 2060
  72. - .cfi_offset hie, 2064
  73. - .cfi_offset htvec, 2068
  74. - .cfi_offset hscratch, 2304
  75. - .cfi_offset hepc, 2308
  76. - .cfi_offset hcause, 2312
  77. - .cfi_offset hbadaddr, 2316
  78. - .cfi_offset hip, 2320
  79. .cfi_offset mbase, 3584
  80. .cfi_offset mbound, 3588
  81. .cfi_offset mibase, 3592
  82. diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l
  83. index 983f593fd7..a735f114ab 100644
  84. --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l
  85. +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l
  86. @@ -5,16 +5,6 @@
  87. .*Warning: Invalid CSR `sptbr' for the privilege spec `1.10'
  88. .*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.10'
  89. .*Warning: Invalid CSR `mucounteren' for the privilege spec `1.10'
  90. -.*Warning: Invalid CSR `hstatus' for the privilege spec `1.10'
  91. -.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.10'
  92. -.*Warning: Invalid CSR `hideleg' for the privilege spec `1.10'
  93. -.*Warning: Invalid CSR `hie' for the privilege spec `1.10'
  94. -.*Warning: Invalid CSR `htvec' for the privilege spec `1.10'
  95. -.*Warning: Invalid CSR `hscratch' for the privilege spec `1.10'
  96. -.*Warning: Invalid CSR `hepc' for the privilege spec `1.10'
  97. -.*Warning: Invalid CSR `hcause' for the privilege spec `1.10'
  98. -.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.10'
  99. -.*Warning: Invalid CSR `hip' for the privilege spec `1.10'
  100. .*Warning: Invalid CSR `mbase' for the privilege spec `1.10'
  101. .*Warning: Invalid CSR `mbound' for the privilege spec `1.10'
  102. .*Warning: Invalid CSR `mibase' for the privilege spec `1.10'
  103. diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l
  104. index 0e036e48e9..bf14859996 100644
  105. --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l
  106. +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l
  107. @@ -4,16 +4,6 @@
  108. .*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
  109. .*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
  110. .*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
  111. -.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
  112. -.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
  113. -.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
  114. -.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
  115. -.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
  116. -.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
  117. -.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
  118. -.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
  119. -.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
  120. -.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
  121. .*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
  122. .*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
  123. .*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
  124. diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
  125. index 3ad8eebe85..caa008feaf 100644
  126. --- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
  127. +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
  128. @@ -225,16 +225,6 @@ Disassembly of section .text:
  129. [ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
  130. [ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
  131. [ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,0x320
  132. -[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,0x200
  133. -[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,0x202
  134. -[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,0x203
  135. -[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,0x204
  136. -[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,0x205
  137. -[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,0x240
  138. -[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,0x241
  139. -[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,0x242
  140. -[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,0x243
  141. -[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,0x244
  142. [ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,0x380
  143. [ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,0x381
  144. [ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,0x382
  145. diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
  146. index 5824bc5e1f..d16a55e5f3 100644
  147. --- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
  148. +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
  149. @@ -225,16 +225,6 @@ Disassembly of section .text:
  150. [ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
  151. [ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
  152. [ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
  153. -[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,0x200
  154. -[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,0x202
  155. -[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,0x203
  156. -[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,0x204
  157. -[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,0x205
  158. -[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,0x240
  159. -[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,0x241
  160. -[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,0x242
  161. -[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,0x243
  162. -[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,0x244
  163. [ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,0x380
  164. [ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,0x381
  165. [ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,0x382
  166. diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
  167. index c40d28862b..30972de834 100644
  168. --- a/gas/testsuite/gas/riscv/priv-reg.s
  169. +++ b/gas/testsuite/gas/riscv/priv-reg.s
  170. @@ -234,16 +234,6 @@
  171. csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
  172. csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
  173. - csr hstatus # 0x200, dropped in 1.10
  174. - csr hedeleg # 0x202, dropped in 1.10
  175. - csr hideleg # 0x203, dropped in 1.10
  176. - csr hie # 0x204, dropped in 1.10
  177. - csr htvec # 0x205, dropped in 1.10
  178. - csr hscratch # 0x240, dropped in 1.10
  179. - csr hepc # 0x241, dropped in 1.10
  180. - csr hcause # 0x242, dropped in 1.10
  181. - csr hbadaddr # 0x243, dropped in 1.10
  182. - csr hip # 0x244, dropped in 1.10
  183. csr mbase # 0x380, dropped in 1.10
  184. csr mbound # 0x381, dropped in 1.10
  185. csr mibase # 0x382, dropped in 1.10
  186. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  187. index 0c23fac724..eea10e1ebc 100644
  188. --- a/include/opcode/riscv-opc.h
  189. +++ b/include/opcode/riscv-opc.h
  190. @@ -2874,16 +2874,6 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
  191. #define CSR_MHPMEVENT29 0x33d
  192. #define CSR_MHPMEVENT30 0x33e
  193. #define CSR_MHPMEVENT31 0x33f
  194. -#define CSR_HSTATUS 0x200
  195. -#define CSR_HEDELEG 0x202
  196. -#define CSR_HIDELEG 0x203
  197. -#define CSR_HIE 0x204
  198. -#define CSR_HTVEC 0x205
  199. -#define CSR_HSCRATCH 0x240
  200. -#define CSR_HEPC 0x241
  201. -#define CSR_HCAUSE 0x242
  202. -#define CSR_HBADADDR 0x243
  203. -#define CSR_HIP 0x244
  204. #define CSR_MBASE 0x380
  205. #define CSR_MBOUND 0x381
  206. #define CSR_MIBASE 0x382
  207. @@ -3526,16 +3516,6 @@ DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR
  208. DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
  209. DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
  210. /* Dropped. */
  211. -DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  212. -DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  213. -DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  214. -DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  215. -DECLARE_CSR(htvec, CSR_HTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  216. -DECLARE_CSR(hscratch, CSR_HSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  217. -DECLARE_CSR(hepc, CSR_HEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  218. -DECLARE_CSR(hcause, CSR_HCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  219. -DECLARE_CSR(hbadaddr, CSR_HBADADDR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  220. -DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  221. DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  222. DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  223. DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  224. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
  225. index c90fc16f34..ee0d277031 100644
  226. --- a/include/opcode/riscv.h
  227. +++ b/include/opcode/riscv.h
  228. @@ -171,6 +171,15 @@ static const char * const riscv_vma[2] =
  229. ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
  230. #define ENCODE_RVC_J_IMM(x) \
  231. ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
  232. +#define ENCODE_RVV_VB_IMM(x) \
  233. + (RV_X(x, 0, 10) << 20)
  234. +#define ENCODE_RVV_VC_IMM(x) \
  235. + (RV_X(x, 0, 11) << 20)
  236. +#define ENCODE_PREF_TIMM(x) \
  237. + (RV_X(x, 0, 4) << 20)
  238. +#define ENCODE_PREF_SIMM(x) \
  239. + (RV_X(x, 0, 8) << 24)
  240. +
  241. #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
  242. #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
  243. @@ -191,6 +200,9 @@ static const char * const riscv_vma[2] =
  244. #define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
  245. #define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
  246. #define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
  247. +#define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x))
  248. +#define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
  249. +
  250. #define RISCV_RTYPE(insn, rd, rs1, rs2) \
  251. ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
  252. @@ -451,6 +463,7 @@ enum riscv_csr_class
  253. CSR_CLASS_I,
  254. CSR_CLASS_I_32, /* rv32 only */
  255. CSR_CLASS_F, /* f-ext only */
  256. + CSR_CLASS_V,
  257. CSR_CLASS_DEBUG /* debug CSR */
  258. };
  259. --
  260. 2.33.1