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- From 51596716546e1ffa485bc2f202d3231177ceffc3 Mon Sep 17 00:00:00 2001
- From: "yilun.xie" <yilun.xie@starfivetech.com>
- Date: Tue, 6 Dec 2022 19:39:16 -0800
- Subject: [PATCH 1/3] add Custom CSR instructions
- ---
- include/opcode/riscv-opc.h | 16 ++++++++++++++++
- opcodes/riscv-opc.c | 6 ++++++
- 2 files changed, 22 insertions(+)
- diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
- index 06e3df0f5a..879eee8471 100644
- --- a/include/opcode/riscv-opc.h
- +++ b/include/opcode/riscv-opc.h
- @@ -267,6 +267,16 @@
- #define MASK_CSRRSI 0x707f
- #define MATCH_CSRRCI 0x7073
- #define MASK_CSRRCI 0x707f
- +/* Custom CSR instruction */
- +#define MATCH_CFLUSH_D_L1 0xfc000073
- +#define MASK_CFLUSH_D_L1 0xfff07fff
- +#define MATCH_CDISCARD_D_L1 0xfc200073
- +#define MASK_CDISCARD_D_L1 0xfff07fff
- +#define MATCH_CFLUSH_D_L2 0xfc400073
- +#define MASK_CFLUSH_D_L2 0xfff07fff
- +#define MATCH_CDISCARD_D_L2 0xfc600073
- +#define MASK_CDISCARD_D_L2 0xfff07fff
- +/**************************************/
- #define MATCH_FADD_S 0x53
- #define MASK_FADD_S 0xfe00007f
- #define MATCH_FSUB_S 0x8000053
- @@ -2905,6 +2915,12 @@ DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
- DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
- DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
- DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
- +/* Custom CSR instruction */
- +DECLARE_INSN(cflush_d_l1, MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1)
- +DECLARE_INSN(cdiscard_d_l1, MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1)
- +DECLARE_INSN(cflush_d_l2, MATCH_CFLUSH_D_L2, MASK_CFLUSH_D_L2)
- +DECLARE_INSN(cdiscard_d_l2, MATCH_CDISCARD_D_L2, MASK_CDISCARD_D_L2)
- +/*******************************************************************/
- DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
- DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
- DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
- index 0e691544f9..f4d1cda8b9 100644
- --- a/opcodes/riscv-opc.c
- +++ b/opcodes/riscv-opc.c
- @@ -929,6 +929,12 @@ const struct riscv_opcode riscv_opcodes[] =
- {"c.fswsp", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE },
- {"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
-
- +/* Custom CSR instruction */
- +{"cflush.d.l1", 0, INSN_CLASS_ZICSR, "s", MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1, match_opcode, 0 },
- +{"cdiscard.d.l1", 0, INSN_CLASS_ZICSR, "s", MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1, match_opcode, 0 },
- +{"cflush.d.l2", 0, INSN_CLASS_ZICSR, "s", MATCH_CFLUSH_D_L2, MASK_CFLUSH_D_L2, match_opcode, 0 },
- +{"cdiscard.d.l2", 0, INSN_CLASS_ZICSR, "s", MATCH_CDISCARD_D_L2, MASK_CDISCARD_D_L2, match_opcode, 0 },
- +/**********************************************************************************************************/
- /* Zicbom and Zicboz instructions. */
- {"cbo.clean", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
- {"cbo.flush", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
- --
- 2.25.1
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