0009-target-riscv-rvb-add-CRC-bit-matrix-instructions.patch 8.5 KB

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  1. From c3c43d0d0a746b557ca2cf647c7181f8e8aa9b20 Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Fri, 9 Jul 2021 17:27:44 +0800
  4. Subject: [PATCH 09/11] target/riscv: rvb: add CRC & bit matrix instructions
  5. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  6. ---
  7. target/riscv/bitmanip_helper.c | 137 ++++++++++++++++++++++++
  8. target/riscv/helper.h | 11 ++
  9. target/riscv/insn32.decode | 11 ++
  10. target/riscv/insn_trans/trans_rvb.c.inc | 37 +++++++
  11. 4 files changed, 196 insertions(+)
  12. diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
  13. index 5e46b69159..7303f42ccb 100644
  14. --- a/target/riscv/bitmanip_helper.c
  15. +++ b/target/riscv/bitmanip_helper.c
  16. @@ -440,3 +440,140 @@ target_ulong HELPER(bdecompress)(target_ulong rs1, target_ulong rs2)
  17. {
  18. return do_bdecompress(rs1, rs2, TARGET_LONG_BITS);
  19. }
  20. +
  21. +#define DO_CRC(NAME, VALUE) \
  22. +static target_ulong do_##NAME(target_ulong rs1, \
  23. + int nbits) \
  24. +{ \
  25. + int i; \
  26. + target_ulong x = rs1; \
  27. + for (i = 0; i < nbits; i++) \
  28. + x = (x >> 1) ^ ((VALUE) & ~((x&1)-1)); \
  29. + return x; \
  30. +}
  31. +
  32. +DO_CRC(crc32, 0xEDB88320)
  33. +DO_CRC(crc32c, 0x82F63B78)
  34. +
  35. +target_ulong HELPER(crc32_b)(target_ulong rs1)
  36. +{
  37. + return do_crc32(rs1, 8);
  38. +}
  39. +
  40. +target_ulong HELPER(crc32_h)(target_ulong rs1)
  41. +{
  42. + return do_crc32(rs1, 16);
  43. +}
  44. +
  45. +target_ulong HELPER(crc32_w)(target_ulong rs1)
  46. +{
  47. + return do_crc32(rs1, 32);
  48. +}
  49. +
  50. +target_ulong HELPER(crc32_d)(target_ulong rs1)
  51. +{
  52. + return do_crc32(rs1, 64);
  53. +}
  54. +
  55. +target_ulong HELPER(crc32c_b)(target_ulong rs1)
  56. +{
  57. + return do_crc32c(rs1, 8);
  58. +}
  59. +
  60. +target_ulong HELPER(crc32c_h)(target_ulong rs1)
  61. +{
  62. + return do_crc32c(rs1, 16);
  63. +}
  64. +
  65. +target_ulong HELPER(crc32c_w)(target_ulong rs1)
  66. +{
  67. + return do_crc32c(rs1, 32);
  68. +}
  69. +
  70. +target_ulong HELPER(crc32c_d)(target_ulong rs1)
  71. +{
  72. + return do_crc32c(rs1, 64);
  73. +}
  74. +
  75. +static inline uint64_t popcount(uint64_t val)
  76. +{
  77. + val = (val & 0x5555555555555555U) + ((val >> 1) & 0x5555555555555555U);
  78. + val = (val & 0x3333333333333333U) + ((val >> 2) & 0x3333333333333333U);
  79. + val = (val & 0x0f0f0f0f0f0f0f0fU) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fU);
  80. + val = (val & 0x00ff00ff00ff00ffU) + ((val >> 8) & 0x00ff00ff00ff00ffU);
  81. + val = (val & 0x0000ffff0000ffffU) + ((val >> 16) & 0x0000ffff0000ffffU);
  82. + val = (val & 0x00000000ffffffffU) + ((val >> 32) & 0x00000000ffffffffU);
  83. + return val;
  84. +}
  85. +
  86. +static target_ulong do_bmatflip(target_ulong rs1,
  87. + int bits)
  88. +{
  89. + target_ulong x = rs1;
  90. + for (int i = 0; i < 3; i++)
  91. + x = do_shfl(x, 31, bits);
  92. + return x;
  93. +}
  94. +
  95. +static target_ulong do_bmatxor(target_ulong rs1,
  96. + target_ulong rs2,
  97. + int bits)
  98. +{
  99. + int i;
  100. + uint8_t u[8];
  101. + uint8_t v[8];
  102. + uint64_t x = 0;
  103. +
  104. + target_ulong rs2t = do_bmatflip(rs2, bits);
  105. +
  106. + for (i = 0; i < 8; i++) {
  107. + u[i] = rs1 >> (i * 8);
  108. + v[i] = rs2t >> (i * 8);
  109. + }
  110. +
  111. + for (int i = 0; i < 64; i++) {
  112. + if (popcount(u[i / 8] & v[i % 8]) & 1)
  113. + x |= 1LL << i;
  114. + }
  115. +
  116. + return x;
  117. +}
  118. +
  119. +static target_ulong do_bmator(target_ulong rs1,
  120. + target_ulong rs2,
  121. + int bits)
  122. +{
  123. + int i;
  124. + uint8_t u[8];
  125. + uint8_t v[8];
  126. + uint64_t x = 0;
  127. +
  128. + target_ulong rs2t = do_bmatflip(rs2, bits);
  129. +
  130. + for (i = 0; i < 8; i++) {
  131. + u[i] = rs1 >> (i * 8);
  132. + v[i] = rs2t >> (i * 8);
  133. + }
  134. +
  135. + for (int i = 0; i < 64; i++) {
  136. + if ((u[i / 8] & v[i % 8]) != 0)
  137. + x |= 1LL << i;
  138. + }
  139. +
  140. + return x;
  141. +}
  142. +
  143. +target_ulong HELPER(bmatflip)(target_ulong rs1)
  144. +{
  145. + return do_bmatflip(rs1, TARGET_LONG_BITS);
  146. +}
  147. +
  148. +target_ulong HELPER(bmatxor)(target_ulong rs1, target_ulong rs2)
  149. +{
  150. + return do_bmatxor(rs1, rs2, TARGET_LONG_BITS);
  151. +}
  152. +
  153. +target_ulong HELPER(bmator)(target_ulong rs1, target_ulong rs2)
  154. +{
  155. + return do_bmator(rs1, rs2, TARGET_LONG_BITS);
  156. +}
  157. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  158. index 577f9f6811..815609c084 100644
  159. --- a/target/riscv/helper.h
  160. +++ b/target/riscv/helper.h
  161. @@ -78,6 +78,17 @@ DEF_HELPER_FLAGS_2(bfp, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  162. DEF_HELPER_FLAGS_2(bfpw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  163. DEF_HELPER_FLAGS_2(bcompress, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  164. DEF_HELPER_FLAGS_2(bdecompress, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  165. +DEF_HELPER_FLAGS_2(bmatxor, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  166. +DEF_HELPER_FLAGS_2(bmator, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  167. +DEF_HELPER_FLAGS_1(bmatflip, TCG_CALL_NO_RWG_SE, tl, tl)
  168. +DEF_HELPER_FLAGS_1(crc32_b, TCG_CALL_NO_RWG_SE, tl, tl)
  169. +DEF_HELPER_FLAGS_1(crc32_h, TCG_CALL_NO_RWG_SE, tl, tl)
  170. +DEF_HELPER_FLAGS_1(crc32_w, TCG_CALL_NO_RWG_SE, tl, tl)
  171. +DEF_HELPER_FLAGS_1(crc32_d, TCG_CALL_NO_RWG_SE, tl, tl)
  172. +DEF_HELPER_FLAGS_1(crc32c_b, TCG_CALL_NO_RWG_SE, tl, tl)
  173. +DEF_HELPER_FLAGS_1(crc32c_h, TCG_CALL_NO_RWG_SE, tl, tl)
  174. +DEF_HELPER_FLAGS_1(crc32c_w, TCG_CALL_NO_RWG_SE, tl, tl)
  175. +DEF_HELPER_FLAGS_1(crc32c_d, TCG_CALL_NO_RWG_SE, tl, tl)
  176. DEF_HELPER_FLAGS_3(cmov, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  177. DEF_HELPER_FLAGS_3(fsl, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  178. DEF_HELPER_FLAGS_3(fsr, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  179. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  180. index 8aaca89ce9..55dc56aa2a 100644
  181. --- a/target/riscv/insn32.decode
  182. +++ b/target/riscv/insn32.decode
  183. @@ -670,8 +670,17 @@ vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
  184. clz 011000 000000 ..... 001 ..... 0010011 @r2
  185. ctz 011000 000001 ..... 001 ..... 0010011 @r2
  186. cpop 011000 000010 ..... 001 ..... 0010011 @r2
  187. +bmatflip 011000 000011 ..... 001 ..... 0010011 @r2
  188. sext_b 011000 000100 ..... 001 ..... 0010011 @r2
  189. sext_h 011000 000101 ..... 001 ..... 0010011 @r2
  190. +crc32_b 0110000 10000 ..... 001 ..... 0010011 @r2
  191. +crc32_h 0110000 10001 ..... 001 ..... 0010011 @r2
  192. +crc32_w 0110000 10010 ..... 001 ..... 0010011 @r2
  193. +crc32_d 0110000 10011 ..... 001 ..... 0010011 @r2
  194. +crc32c_b 0110000 11000 ..... 001 ..... 0010011 @r2
  195. +crc32c_h 0110000 11001 ..... 001 ..... 0010011 @r2
  196. +crc32c_w 0110000 11010 ..... 001 ..... 0010011 @r2
  197. +crc32c_d 0110000 11011 ..... 001 ..... 0010011 @r2
  198. andn 0100000 .......... 111 ..... 0110011 @r
  199. orn 0100000 .......... 110 ..... 0110011 @r
  200. @@ -711,6 +720,8 @@ fsl .....10 .......... 001 ..... 0110011 @r3
  201. fsr .....10 .......... 101 ..... 0110011 @r3
  202. bcompress 0000100 .......... 110 ..... 0110011 @r
  203. bdecompress 0100100 .......... 110 ..... 0110011 @r
  204. +bmator 0000100 .......... 011 ..... 0110011 @r
  205. +bmatxor 0100100 .......... 011 ..... 0110011 @r
  206. fsri .....1 ........... 101 ..... 0010011 @r3_imm
  207. bseti 001010 ........... 001 ..... 0010011 @sh6
  208. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  209. index d4374d174e..fde91c1953 100644
  210. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  211. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  212. @@ -408,6 +408,43 @@ static bool trans_bdecompressw(DisasContext *ctx, arg_bdecompressw *a)
  213. return gen_arith(ctx, a, gen_bdecompressw);
  214. }
  215. +#define GEN_TRANS_CRC(NAME) \
  216. +static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
  217. +{ \
  218. + REQUIRE_EXT(ctx, RVB); \
  219. + return gen_unary(ctx, a, gen_helper_##NAME); \
  220. +} \
  221. +
  222. +GEN_TRANS_CRC(crc32_b)
  223. +GEN_TRANS_CRC(crc32_h)
  224. +GEN_TRANS_CRC(crc32_w)
  225. +GEN_TRANS_CRC(crc32_d)
  226. +GEN_TRANS_CRC(crc32c_b)
  227. +GEN_TRANS_CRC(crc32c_h)
  228. +GEN_TRANS_CRC(crc32c_w)
  229. +GEN_TRANS_CRC(crc32c_d)
  230. +
  231. +static bool trans_bmatflip(DisasContext *ctx, arg_bmatflip *a)
  232. +{
  233. + REQUIRE_64BIT(ctx);
  234. + REQUIRE_EXT(ctx, RVB);
  235. + return gen_unary(ctx, a, gen_helper_bmatflip);
  236. +}
  237. +
  238. +static bool trans_bmatxor(DisasContext *ctx, arg_bmatxor *a)
  239. +{
  240. + REQUIRE_64BIT(ctx);
  241. + REQUIRE_EXT(ctx, RVB);
  242. + return gen_arith(ctx, a, gen_helper_bmatxor);
  243. +}
  244. +
  245. +static bool trans_bmator(DisasContext *ctx, arg_bmatxor *a)
  246. +{
  247. + REQUIRE_64BIT(ctx);
  248. + REQUIRE_EXT(ctx, RVB);
  249. + return gen_arith(ctx, a, gen_helper_bmator);
  250. +}
  251. +
  252. static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
  253. {
  254. REQUIRE_64BIT(ctx);
  255. --
  256. 2.33.0