0006-target-riscv-rvb-add-bfp-bfpw-instructions.patch 5.3 KB

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  1. From 27fd4ca5ae5a5cd8ba49482305d54961a2031932 Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Fri, 9 Jul 2021 12:36:57 +0800
  4. Subject: [PATCH 06/11] target/riscv: rvb: add bfp/bfpw instructions
  5. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  6. ---
  7. target/riscv/bitmanip_helper.c | 40 ++++++++++++++++++++++++-
  8. target/riscv/helper.h | 2 ++
  9. target/riscv/insn32.decode | 2 ++
  10. target/riscv/insn_trans/trans_rvb.c.inc | 13 ++++++++
  11. target/riscv/translate.c | 6 ++++
  12. 5 files changed, 62 insertions(+), 1 deletion(-)
  13. diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
  14. index 6185fe44d3..a610b22fa6 100644
  15. --- a/target/riscv/bitmanip_helper.c
  16. +++ b/target/riscv/bitmanip_helper.c
  17. @@ -135,7 +135,6 @@ target_ulong HELPER(cmov)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
  18. return do_cmov(rs1, rs2, rs3);
  19. }
  20. -
  21. static target_ulong do_fsl(target_ulong rs1,
  22. target_ulong rs2,
  23. target_ulong rs3,
  24. @@ -359,3 +358,42 @@ target_ulong HELPER(xperm_w)(target_ulong rs1, target_ulong rs2)
  25. {
  26. return do_xperm(rs1, rs2, 5, TARGET_LONG_BITS);
  27. }
  28. +
  29. +static target_ulong do_bfp(target_ulong rs1,
  30. + target_ulong rs2,
  31. + int bits)
  32. +{
  33. + target_ulong cfg = rs2 >> (bits/2);
  34. + if ((cfg >> 30) == 2)
  35. + cfg = cfg >> 16;
  36. + int len = (cfg >> 8) & (bits/2 - 1);
  37. + int off = cfg & (bits - 1);
  38. + len = len ? len : bits/2;
  39. + target_ulong mask = ~(~(target_ulong)0 << len) << off;
  40. + target_ulong data = rs2 << off;
  41. +
  42. + return (data & mask) | (rs1 & ~mask);
  43. +}
  44. +
  45. +static target_ulong do_bfpw(target_ulong rs1,
  46. + target_ulong rs2)
  47. +{
  48. + target_ulong cfg = rs2 >> 16;
  49. + int len = (cfg >> 8) & 15;
  50. + int off = cfg & 31;
  51. + len = len ? len : 16;
  52. + target_ulong mask = ~(~(target_ulong)(0) << len) << off;
  53. + target_ulong data = rs2 << off;
  54. +
  55. + return (data & mask) | (rs1 & ~mask);
  56. +}
  57. +
  58. +target_ulong HELPER(bfp)(target_ulong rs1, target_ulong rs2)
  59. +{
  60. + return do_bfp(rs1, rs2, TARGET_LONG_BITS);
  61. +}
  62. +
  63. +target_ulong HELPER(bfpw)(target_ulong rs1, target_ulong rs2)
  64. +{
  65. + return do_bfpw(rs1, rs2);
  66. +}
  67. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  68. index 2e6d4c3704..2ae199f399 100644
  69. --- a/target/riscv/helper.h
  70. +++ b/target/riscv/helper.h
  71. @@ -74,6 +74,8 @@ DEF_HELPER_FLAGS_2(xperm_n, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  72. DEF_HELPER_FLAGS_2(xperm_b, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  73. DEF_HELPER_FLAGS_2(xperm_h, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  74. DEF_HELPER_FLAGS_2(xperm_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  75. +DEF_HELPER_FLAGS_2(bfp, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  76. +DEF_HELPER_FLAGS_2(bfpw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  77. DEF_HELPER_FLAGS_3(cmov, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  78. DEF_HELPER_FLAGS_3(fsl, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  79. DEF_HELPER_FLAGS_3(fsr, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  80. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  81. index 3fcddcd5e3..8187c42323 100644
  82. --- a/target/riscv/insn32.decode
  83. +++ b/target/riscv/insn32.decode
  84. @@ -704,6 +704,7 @@ unshfl 0000100 .......... 101 ..... 0110011 @r
  85. xperm_n 0010100 .......... 010 ..... 0110011 @r
  86. xperm_b 0010100 .......... 100 ..... 0110011 @r
  87. xperm_h 0010100 .......... 110 ..... 0110011 @r
  88. +bfp 0100100 .......... 111 ..... 0110011 @r
  89. cmix .....11 .......... 001 ..... 0110011 @r3
  90. cmov .....11 .......... 101 ..... 0110011 @r3
  91. fsl .....10 .......... 001 ..... 0110011 @r3
  92. @@ -746,6 +747,7 @@ add_uw 0000100 .......... 000 ..... 0111011 @r
  93. shflw 0000100 .......... 001 ..... 0111011 @r
  94. unshflw 0000100 .......... 101 ..... 0111011 @r
  95. xperm_w 0010100 .......... 000 ..... 0110011 @r
  96. +bfpw 0100100 .......... 111 ..... 0111011 @r
  97. fslw .....10 .......... 001 ..... 0111011 @r3
  98. fsrw .....10 .......... 101 ..... 0111011 @r3
  99. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  100. index 12cfb0d955..e15f0a7999 100644
  101. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  102. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  103. @@ -289,6 +289,12 @@ GEN_TRANS_XPERM(xperm_n)
  104. GEN_TRANS_XPERM(xperm_b)
  105. GEN_TRANS_XPERM(xperm_h)
  106. +static bool trans_bfp(DisasContext *ctx, arg_bfp *a)
  107. +{
  108. + REQUIRE_EXT(ctx, RVB);
  109. + return gen_arith(ctx, a, gen_helper_bfp);
  110. +}
  111. +
  112. static bool trans_cmix(DisasContext *ctx, arg_cmix *a)
  113. {
  114. REQUIRE_EXT(ctx, RVB);
  115. @@ -345,6 +351,13 @@ static bool trans_xperm_w(DisasContext *ctx, arg_xperm_w *a)
  116. return gen_arith(ctx, a, gen_helper_xperm_w);
  117. }
  118. +static bool trans_bfpw(DisasContext *ctx, arg_bfpw *a)
  119. +{
  120. + REQUIRE_64BIT(ctx);
  121. + REQUIRE_EXT(ctx, RVB);
  122. + return gen_arith(ctx, a, gen_bfpw);
  123. +}
  124. +
  125. static bool trans_fslw(DisasContext *ctx, arg_fslw *a)
  126. {
  127. REQUIRE_64BIT(ctx);
  128. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  129. index daaffa2b26..37eb0ea046 100644
  130. --- a/target/riscv/translate.c
  131. +++ b/target/riscv/translate.c
  132. @@ -857,6 +857,12 @@ static bool gen_quati(DisasContext *ctx, arg_r3i *a,
  133. return true;
  134. }
  135. +static void gen_bfpw(TCGv ret, TCGv arg1, TCGv arg2)
  136. +{
  137. + gen_helper_bfpw(ret, arg1, arg2);
  138. + tcg_gen_ext32s_tl(ret, ret);
  139. +}
  140. +
  141. static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
  142. {
  143. DisasContext *ctx = container_of(dcbase, DisasContext, base);
  144. --
  145. 2.33.0