0005-target-riscv-rvb-add-crossbar-permutation-instructio.patch 5.0 KB

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  1. From 8aee0b0ae5bf3becd7544e0ed0694268ccaf135a Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Fri, 9 Jul 2021 11:02:06 +0800
  4. Subject: [PATCH 05/11] target/riscv: rvb: add crossbar permutation
  5. instructions
  6. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  7. ---
  8. target/riscv/bitmanip_helper.c | 39 +++++++++++++++++++++++++
  9. target/riscv/helper.h | 4 +++
  10. target/riscv/insn32.decode | 4 +++
  11. target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++
  12. 4 files changed, 65 insertions(+)
  13. diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
  14. index 0e4780a4cb..6185fe44d3 100644
  15. --- a/target/riscv/bitmanip_helper.c
  16. +++ b/target/riscv/bitmanip_helper.c
  17. @@ -320,3 +320,42 @@ target_ulong HELPER(unshflw)(target_ulong rs1, target_ulong rs2)
  18. {
  19. return do_unshflw(rs1, rs2, TARGET_LONG_BITS);
  20. }
  21. +
  22. +static target_ulong do_xperm(target_ulong rs1,
  23. + target_ulong rs2,
  24. + int sz_log2,
  25. + int bits)
  26. +{
  27. + target_ulong pos = 0;
  28. + target_ulong r = 0;
  29. + target_ulong sz = 1LL << sz_log2;
  30. + target_ulong mask = (1LL << sz) - 1;
  31. + int i;
  32. + for (i = 0; i < bits; i += sz) {
  33. + pos = ((rs2 >> i) & mask) << sz_log2;
  34. + if (pos < bits)
  35. + r |= ((rs1 >> pos) & mask) << i;
  36. + }
  37. +
  38. + return r;
  39. +}
  40. +
  41. +target_ulong HELPER(xperm_n)(target_ulong rs1, target_ulong rs2)
  42. +{
  43. + return do_xperm(rs1, rs2, 2, TARGET_LONG_BITS);
  44. +}
  45. +
  46. +target_ulong HELPER(xperm_b)(target_ulong rs1, target_ulong rs2)
  47. +{
  48. + return do_xperm(rs1, rs2, 3, TARGET_LONG_BITS);
  49. +}
  50. +
  51. +target_ulong HELPER(xperm_h)(target_ulong rs1, target_ulong rs2)
  52. +{
  53. + return do_xperm(rs1, rs2, 4, TARGET_LONG_BITS);
  54. +}
  55. +
  56. +target_ulong HELPER(xperm_w)(target_ulong rs1, target_ulong rs2)
  57. +{
  58. + return do_xperm(rs1, rs2, 5, TARGET_LONG_BITS);
  59. +}
  60. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  61. index 8190b72880..2e6d4c3704 100644
  62. --- a/target/riscv/helper.h
  63. +++ b/target/riscv/helper.h
  64. @@ -70,6 +70,10 @@ DEF_HELPER_FLAGS_2(shfl, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  65. DEF_HELPER_FLAGS_2(unshfl, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  66. DEF_HELPER_FLAGS_2(shflw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  67. DEF_HELPER_FLAGS_2(unshflw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  68. +DEF_HELPER_FLAGS_2(xperm_n, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  69. +DEF_HELPER_FLAGS_2(xperm_b, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  70. +DEF_HELPER_FLAGS_2(xperm_h, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  71. +DEF_HELPER_FLAGS_2(xperm_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  72. DEF_HELPER_FLAGS_3(cmov, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  73. DEF_HELPER_FLAGS_3(fsl, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  74. DEF_HELPER_FLAGS_3(fsr, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  75. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  76. index cd3518d716..3fcddcd5e3 100644
  77. --- a/target/riscv/insn32.decode
  78. +++ b/target/riscv/insn32.decode
  79. @@ -701,6 +701,9 @@ clmulh 0000101 .......... 011 ..... 0110011 @r
  80. clmulr 0000101 .......... 010 ..... 0110011 @r
  81. shfl 0000100 .......... 001 ..... 0110011 @r
  82. unshfl 0000100 .......... 101 ..... 0110011 @r
  83. +xperm_n 0010100 .......... 010 ..... 0110011 @r
  84. +xperm_b 0010100 .......... 100 ..... 0110011 @r
  85. +xperm_h 0010100 .......... 110 ..... 0110011 @r
  86. cmix .....11 .......... 001 ..... 0110011 @r3
  87. cmov .....11 .......... 101 ..... 0110011 @r3
  88. fsl .....10 .......... 001 ..... 0110011 @r3
  89. @@ -742,6 +745,7 @@ sh3add_uw 0010000 .......... 110 ..... 0111011 @r
  90. add_uw 0000100 .......... 000 ..... 0111011 @r
  91. shflw 0000100 .......... 001 ..... 0111011 @r
  92. unshflw 0000100 .......... 101 ..... 0111011 @r
  93. +xperm_w 0010100 .......... 000 ..... 0110011 @r
  94. fslw .....10 .......... 001 ..... 0111011 @r3
  95. fsrw .....10 .......... 101 ..... 0111011 @r3
  96. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  97. index 4317a8b2db..12cfb0d955 100644
  98. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  99. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  100. @@ -278,6 +278,17 @@ static bool trans_unshfli(DisasContext *ctx, arg_unshfli *a)
  101. return gen_shifti(ctx, a, gen_helper_unshfl);
  102. }
  103. +#define GEN_TRANS_XPERM(NAME) \
  104. +static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
  105. +{ \
  106. + REQUIRE_EXT(ctx, RVB); \
  107. + return gen_arith(ctx, a, gen_helper_##NAME); \
  108. +}
  109. +
  110. +GEN_TRANS_XPERM(xperm_n)
  111. +GEN_TRANS_XPERM(xperm_b)
  112. +GEN_TRANS_XPERM(xperm_h)
  113. +
  114. static bool trans_cmix(DisasContext *ctx, arg_cmix *a)
  115. {
  116. REQUIRE_EXT(ctx, RVB);
  117. @@ -327,6 +338,13 @@ static bool trans_unshflw(DisasContext *ctx, arg_unshflw *a)
  118. return gen_arith(ctx, a, gen_helper_unshflw);
  119. }
  120. +static bool trans_xperm_w(DisasContext *ctx, arg_xperm_w *a)
  121. +{
  122. + REQUIRE_64BIT(ctx);
  123. + REQUIRE_EXT(ctx, RVB);
  124. + return gen_arith(ctx, a, gen_helper_xperm_w);
  125. +}
  126. +
  127. static bool trans_fslw(DisasContext *ctx, arg_fslw *a)
  128. {
  129. REQUIRE_64BIT(ctx);
  130. --
  131. 2.33.0