0004-target-riscv-rvb-add-generalized-shuffle.patch 9.0 KB

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  1. From ff1e4f73a392660a0f9f9a728c199caadfe9aefe Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Fri, 9 Jul 2021 10:13:36 +0800
  4. Subject: [PATCH 04/11] target/riscv: rvb: add generalized shuffle
  5. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  6. ---
  7. target/riscv/bitmanip_helper.c | 132 ++++++++++++++++++++++++
  8. target/riscv/helper.h | 4 +
  9. target/riscv/insn32.decode | 6 ++
  10. target/riscv/insn_trans/trans_rvb.c.inc | 44 ++++++++
  11. 4 files changed, 186 insertions(+)
  12. diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
  13. index b90bdafb62..0e4780a4cb 100644
  14. --- a/target/riscv/bitmanip_helper.c
  15. +++ b/target/riscv/bitmanip_helper.c
  16. @@ -188,3 +188,135 @@ target_ulong HELPER(fsrw)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
  17. {
  18. return do_fslw(rs1, -rs2, rs3);
  19. }
  20. +static target_ulong do_shfl(target_ulong rs1,
  21. + target_ulong rs2,
  22. + int bits)
  23. +{
  24. + target_ulong x = rs1;
  25. + int shamt = rs2 & ((bits-1) >> 1);
  26. + if (shamt & 16)
  27. + x = (x & 0xFFFF00000000FFFFLL) |
  28. + ((x & 0x0000FFFF00000000LL) >> 16) |
  29. + ((x & 0x00000000FFFF0000LL) << 16);
  30. + if (shamt & 8)
  31. + x = (x & 0xFF0000FFFF0000FFLL) |
  32. + ((x & 0x00FF000000FF0000LL) >> 8) |
  33. + ((x & 0x0000FF000000FF00LL) << 8);
  34. + if (shamt & 4)
  35. + x = (x & 0xF00FF00FF00FF00FLL) |
  36. + ((x & 0x0F000F000F000F00LL) >> 4) |
  37. + ((x & 0x00F000F000F000F0LL) << 4);
  38. + if (shamt & 2)
  39. + x = (x & 0xC3C3C3C3C3C3C3C3LL) |
  40. + ((x & 0x3030303030303030LL) >> 2) |
  41. + ((x & 0x0C0C0C0C0C0C0C0CLL) << 2);
  42. + if (shamt & 1)
  43. + x = (x & 0x9999999999999999LL) |
  44. + ((x & 0x4444444444444444LL) >> 1) |
  45. + ((x & 0x2222222222222222LL) << 1);
  46. +
  47. + return x;
  48. +}
  49. +
  50. +static target_ulong do_unshfl(target_ulong rs1,
  51. + target_ulong rs2,
  52. + int bits)
  53. +{
  54. + target_ulong x = rs1;
  55. +
  56. + int shamt = rs2 & ((bits-1) >> 1);
  57. + if (shamt & 1)
  58. + x = (x & 0x9999999999999999LL) |
  59. + ((x & 0x4444444444444444LL) >> 1) |
  60. + ((x & 0x2222222222222222LL) << 1);
  61. + if (shamt & 2)
  62. + x = (x & 0xC3C3C3C3C3C3C3C3LL) |
  63. + ((x & 0x3030303030303030LL) >> 2) |
  64. + ((x & 0x0C0C0C0C0C0C0C0CLL) << 2);
  65. + if (shamt & 4)
  66. + x = (x & 0xF00FF00FF00FF00FLL) |
  67. + ((x & 0x0F000F000F000F00LL) >> 4) |
  68. + ((x & 0x00F000F000F000F0LL) << 4);
  69. + if (shamt & 8)
  70. + x = (x & 0xFF0000FFFF0000FFLL) |
  71. + ((x & 0x00FF000000FF0000LL) >> 8) |
  72. + ((x & 0x0000FF000000FF00LL) << 8);
  73. + if (shamt & 16)
  74. + x = (x & 0xFFFF00000000FFFFLL) |
  75. + ((x & 0x0000FFFF00000000LL) >> 16) |
  76. + ((x & 0x00000000FFFF0000LL) << 16);
  77. +
  78. + return x;
  79. +}
  80. +
  81. +static target_ulong do_shflw(target_ulong rs1,
  82. + target_ulong rs2,
  83. + int bits)
  84. +{
  85. + target_ulong x = rs1;
  86. + int shamt = rs2 & 15;
  87. + if (shamt & 8)
  88. + x = (x & 0xFF0000FFFF0000FFLL) |
  89. + ((x & 0x00FF000000FF0000LL) >> 8) |
  90. + ((x & 0x0000FF000000FF00LL) << 8);
  91. + if (shamt & 4)
  92. + x = (x & 0xF00FF00FF00FF00FLL) |
  93. + ((x & 0x0F000F000F000F00LL) >> 4) |
  94. + ((x & 0x00F000F000F000F0LL) << 4);
  95. + if (shamt & 2)
  96. + x = (x & 0xC3C3C3C3C3C3C3C3LL) |
  97. + ((x & 0x3030303030303030LL) >> 2) |
  98. + ((x & 0x0C0C0C0C0C0C0C0CLL) << 2);
  99. + if (shamt & 1)
  100. + x = (x & 0x9999999999999999LL) |
  101. + ((x & 0x4444444444444444LL) >> 1) |
  102. + ((x & 0x2222222222222222LL) << 1);
  103. +
  104. + return x;
  105. +}
  106. +
  107. +static target_ulong do_unshflw(target_ulong rs1,
  108. + target_ulong rs2,
  109. + int bits)
  110. +{
  111. + target_ulong x = rs1;
  112. + int shamt = rs2 & 15;
  113. + if (shamt & 1)
  114. + x = (x & 0x9999999999999999LL) |
  115. + ((x & 0x4444444444444444LL) >> 1) |
  116. + ((x & 0x2222222222222222LL) << 1);
  117. + if (shamt & 2)
  118. + x = (x & 0xC3C3C3C3C3C3C3C3LL) |
  119. + ((x & 0x3030303030303030LL) >> 2) |
  120. + ((x & 0x0C0C0C0C0C0C0C0CLL) << 2);
  121. + if (shamt & 4)
  122. + x = (x & 0xF00FF00FF00FF00FLL) |
  123. + ((x & 0x0F000F000F000F00LL) >> 4) |
  124. + ((x & 0x00F000F000F000F0LL) << 4);
  125. + if (shamt & 8)
  126. + x = (x & 0xFF0000FFFF0000FFLL) |
  127. + ((x & 0x00FF000000FF0000LL) >> 8) |
  128. + ((x & 0x0000FF000000FF00LL) << 8);
  129. +
  130. + return x;
  131. +}
  132. +
  133. +target_ulong HELPER(shfl)(target_ulong rs1, target_ulong rs2)
  134. +{
  135. + return do_shfl(rs1, rs2, TARGET_LONG_BITS);
  136. +}
  137. +
  138. +target_ulong HELPER(unshfl)(target_ulong rs1, target_ulong rs2)
  139. +{
  140. + return do_unshfl(rs1, rs2, TARGET_LONG_BITS);
  141. +}
  142. +
  143. +target_ulong HELPER(shflw)(target_ulong rs1, target_ulong rs2)
  144. +{
  145. + return do_shflw(rs1, rs2, TARGET_LONG_BITS);
  146. +}
  147. +
  148. +target_ulong HELPER(unshflw)(target_ulong rs1, target_ulong rs2)
  149. +{
  150. + return do_unshflw(rs1, rs2, TARGET_LONG_BITS);
  151. +}
  152. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  153. index dcf87f2423..8190b72880 100644
  154. --- a/target/riscv/helper.h
  155. +++ b/target/riscv/helper.h
  156. @@ -66,6 +66,10 @@ DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  157. DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  158. DEF_HELPER_FLAGS_2(clmulh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  159. DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  160. +DEF_HELPER_FLAGS_2(shfl, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  161. +DEF_HELPER_FLAGS_2(unshfl, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  162. +DEF_HELPER_FLAGS_2(shflw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  163. +DEF_HELPER_FLAGS_2(unshflw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  164. DEF_HELPER_FLAGS_3(cmov, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  165. DEF_HELPER_FLAGS_3(fsl, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  166. DEF_HELPER_FLAGS_3(fsr, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  167. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  168. index e635b0b6e1..cd3518d716 100644
  169. --- a/target/riscv/insn32.decode
  170. +++ b/target/riscv/insn32.decode
  171. @@ -699,6 +699,8 @@ sh3add 0010000 .......... 110 ..... 0110011 @r
  172. clmul 0000101 .......... 001 ..... 0110011 @r
  173. clmulh 0000101 .......... 011 ..... 0110011 @r
  174. clmulr 0000101 .......... 010 ..... 0110011 @r
  175. +shfl 0000100 .......... 001 ..... 0110011 @r
  176. +unshfl 0000100 .......... 101 ..... 0110011 @r
  177. cmix .....11 .......... 001 ..... 0110011 @r3
  178. cmov .....11 .......... 101 ..... 0110011 @r3
  179. fsl .....10 .......... 001 ..... 0110011 @r3
  180. @@ -714,6 +716,8 @@ sroi 001000 ........... 101 ..... 0010011 @sh6
  181. rori 011000 ........... 101 ..... 0010011 @sh6
  182. grevi 011010 ........... 101 ..... 0010011 @sh6
  183. gorci 001010 ........... 101 ..... 0010011 @sh6
  184. +shfli 000010 ........... 001 ..... 0010011 @sh6
  185. +unshfli 000010 ........... 101 ..... 0010011 @sh6
  186. # *** RV64B Standard Extension (in addition to RV32B) ***
  187. clzw 0110000 00000 ..... 001 ..... 0011011 @r2
  188. @@ -736,6 +740,8 @@ sh1add_uw 0010000 .......... 010 ..... 0111011 @r
  189. sh2add_uw 0010000 .......... 100 ..... 0111011 @r
  190. sh3add_uw 0010000 .......... 110 ..... 0111011 @r
  191. add_uw 0000100 .......... 000 ..... 0111011 @r
  192. +shflw 0000100 .......... 001 ..... 0111011 @r
  193. +unshflw 0000100 .......... 101 ..... 0111011 @r
  194. fslw .....10 .......... 001 ..... 0111011 @r3
  195. fsrw .....10 .......... 101 ..... 0111011 @r3
  196. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  197. index 91762aace5..4317a8b2db 100644
  198. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  199. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  200. @@ -248,6 +248,36 @@ GEN_TRANS_CLMUL(clmul)
  201. GEN_TRANS_CLMUL(clmulh)
  202. GEN_TRANS_CLMUL(clmulr)
  203. +static bool trans_shfl(DisasContext *ctx, arg_shfl *a)
  204. +{
  205. + REQUIRE_EXT(ctx, RVB);
  206. + return gen_arith(ctx, a, gen_helper_shfl);
  207. +}
  208. +
  209. +static bool trans_unshfl(DisasContext *ctx, arg_unshfl *a)
  210. +{
  211. + REQUIRE_EXT(ctx, RVB);
  212. + return gen_arith(ctx, a, gen_helper_unshfl);
  213. +}
  214. +
  215. +static bool trans_shfli(DisasContext *ctx, arg_shfli *a)
  216. +{
  217. + REQUIRE_EXT(ctx, RVB);
  218. + if (a->shamt >= (TARGET_LONG_BITS / 2)) {
  219. + return false;
  220. + }
  221. + return gen_shifti(ctx, a, gen_helper_shfl);
  222. +}
  223. +
  224. +static bool trans_unshfli(DisasContext *ctx, arg_unshfli *a)
  225. +{
  226. + REQUIRE_EXT(ctx, RVB);
  227. + if (a->shamt >= (TARGET_LONG_BITS / 2)) {
  228. + return false;
  229. + }
  230. + return gen_shifti(ctx, a, gen_helper_unshfl);
  231. +}
  232. +
  233. static bool trans_cmix(DisasContext *ctx, arg_cmix *a)
  234. {
  235. REQUIRE_EXT(ctx, RVB);
  236. @@ -283,6 +313,20 @@ static bool trans_fsri(DisasContext *ctx, arg_fsri *a)
  237. return gen_quati(ctx, a, gen_helper_fsr);
  238. }
  239. +static bool trans_shflw(DisasContext *ctx, arg_shflw *a)
  240. +{
  241. + REQUIRE_64BIT(ctx);
  242. + REQUIRE_EXT(ctx, RVB);
  243. + return gen_arith(ctx, a, gen_helper_shflw);
  244. +}
  245. +
  246. +static bool trans_unshflw(DisasContext *ctx, arg_unshflw *a)
  247. +{
  248. + REQUIRE_64BIT(ctx);
  249. + REQUIRE_EXT(ctx, RVB);
  250. + return gen_arith(ctx, a, gen_helper_unshflw);
  251. +}
  252. +
  253. static bool trans_fslw(DisasContext *ctx, arg_fslw *a)
  254. {
  255. REQUIRE_64BIT(ctx);
  256. --
  257. 2.33.0