0003-target-riscv-rvb-add-funnel-shfit-instruction.patch 9.4 KB

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  1. From 12b81cda67d951924d9a4ae3b3e430c35a2f7f05 Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Thu, 8 Jul 2021 19:33:13 +0800
  4. Subject: [PATCH 03/11] target/riscv: rvb: add funnel shfit instruction
  5. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  6. ---
  7. target/riscv/bitmanip_helper.c | 54 +++++++++++++++++++++++++
  8. target/riscv/helper.h | 4 ++
  9. target/riscv/insn32.decode | 37 +++++++++++------
  10. target/riscv/insn_trans/trans_rvb.c.inc | 49 ++++++++++++++++++++++
  11. target/riscv/translate.c | 21 ++++++++++
  12. 5 files changed, 152 insertions(+), 13 deletions(-)
  13. diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
  14. index 46b51399f2..b90bdafb62 100644
  15. --- a/target/riscv/bitmanip_helper.c
  16. +++ b/target/riscv/bitmanip_helper.c
  17. @@ -134,3 +134,57 @@ target_ulong HELPER(cmov)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
  18. {
  19. return do_cmov(rs1, rs2, rs3);
  20. }
  21. +
  22. +
  23. +static target_ulong do_fsl(target_ulong rs1,
  24. + target_ulong rs2,
  25. + target_ulong rs3,
  26. + int bits)
  27. +{
  28. + int shamt = rs2 & (2*bits - 1);
  29. + target_ulong a = rs1, b = rs3;
  30. +
  31. + if (shamt >= bits) {
  32. + shamt -= bits;
  33. + a = rs3;
  34. + b = rs1;
  35. + }
  36. +
  37. + return shamt ? (a << shamt) | (b >> (bits - shamt)) : a;
  38. +}
  39. +
  40. +target_ulong HELPER(fsl)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
  41. +{
  42. + return do_fsl(rs1, rs2, rs3, TARGET_LONG_BITS);
  43. +}
  44. +
  45. +target_ulong HELPER(fsr)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
  46. +{
  47. + return do_fsl(rs1, -rs2, rs3, TARGET_LONG_BITS);
  48. +}
  49. +
  50. +static target_ulong do_fslw(target_ulong rs1,
  51. + target_ulong rs2,
  52. + target_ulong rs3)
  53. +{
  54. + int shamt = rs2 & 63;
  55. + target_ulong a = rs1, b = rs3;
  56. +
  57. + if (shamt >= 32) {
  58. + shamt -= 32;
  59. + a = rs3;
  60. + b = rs1;
  61. + }
  62. +
  63. + return shamt ? (a << shamt) | (b >> (32 - shamt)) : a;
  64. +}
  65. +
  66. +target_ulong HELPER(fslw)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
  67. +{
  68. + return do_fslw(rs1, rs2, rs3);
  69. +}
  70. +
  71. +target_ulong HELPER(fsrw)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
  72. +{
  73. + return do_fslw(rs1, -rs2, rs3);
  74. +}
  75. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  76. index 1282aada80..dcf87f2423 100644
  77. --- a/target/riscv/helper.h
  78. +++ b/target/riscv/helper.h
  79. @@ -67,6 +67,10 @@ DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  80. DEF_HELPER_FLAGS_2(clmulh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  81. DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  82. DEF_HELPER_FLAGS_3(cmov, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  83. +DEF_HELPER_FLAGS_3(fsl, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  84. +DEF_HELPER_FLAGS_3(fsr, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  85. +DEF_HELPER_FLAGS_3(fslw, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  86. +DEF_HELPER_FLAGS_3(fsrw, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  87. /* Special functions */
  88. DEF_HELPER_3(csrrw, tl, env, tl, tl)
  89. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  90. index 06527db5f2..e635b0b6e1 100644
  91. --- a/target/riscv/insn32.decode
  92. +++ b/target/riscv/insn32.decode
  93. @@ -24,6 +24,7 @@
  94. %sh5 20:5
  95. %sh7 20:7
  96. +%sh6 20:6
  97. %csr 20:12
  98. %rm 12:3
  99. %nf 29:3 !function=ex_plus_1
  100. @@ -43,6 +44,7 @@
  101. &r rd rs1 rs2
  102. &r2 rd rs1
  103. &r3 rd rs1 rs2 rs3
  104. +&r3i rd rs1 imm rs3
  105. &s imm rs1 rs2
  106. &u imm rd
  107. &shift shamt rs1 rd
  108. @@ -62,12 +64,15 @@
  109. @j .................... ..... ....... &j imm=%imm_j %rd
  110. @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
  111. +@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
  112. @csr ............ ..... ... ..... ....... %csr %rs1 %rd
  113. @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
  114. @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
  115. @r3 ..... .. ..... ..... ... ..... ....... &r3 %rs3 %rs2 %rs1 %rd
  116. +@r3_imm ..... . ...... ..... ... ..... ....... &r3i %rs3 imm=%sh6 %rs1 %rd
  117. +@r3w_imm ..... . ...... ..... ... ..... ....... &r3i %rs3 imm=%sh5 %rs1 %rd
  118. @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
  119. @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
  120. @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
  121. @@ -128,9 +133,9 @@ sltiu ............ ..... 011 ..... 0010011 @i
  122. xori ............ ..... 100 ..... 0010011 @i
  123. ori ............ ..... 110 ..... 0010011 @i
  124. andi ............ ..... 111 ..... 0010011 @i
  125. -slli 00000. ...... ..... 001 ..... 0010011 @sh
  126. -srli 00000. ...... ..... 101 ..... 0010011 @sh
  127. -srai 01000. ...... ..... 101 ..... 0010011 @sh
  128. +slli 000000 ...... ..... 001 ..... 0010011 @sh6
  129. +srli 000000 ...... ..... 101 ..... 0010011 @sh6
  130. +srai 010000 ...... ..... 101 ..... 0010011 @sh6
  131. add 0000000 ..... ..... 000 ..... 0110011 @r
  132. sub 0100000 ..... ..... 000 ..... 0110011 @r
  133. sll 0000000 ..... ..... 001 ..... 0110011 @r
  134. @@ -696,16 +701,19 @@ clmulh 0000101 .......... 011 ..... 0110011 @r
  135. clmulr 0000101 .......... 010 ..... 0110011 @r
  136. cmix .....11 .......... 001 ..... 0110011 @r3
  137. cmov .....11 .......... 101 ..... 0110011 @r3
  138. -
  139. -bseti 00101. ........... 001 ..... 0010011 @sh
  140. -bclri 01001. ........... 001 ..... 0010011 @sh
  141. -binvi 01101. ........... 001 ..... 0010011 @sh
  142. -bexti 01001. ........... 101 ..... 0010011 @sh
  143. -sloi 00100. ........... 001 ..... 0010011 @sh
  144. -sroi 00100. ........... 101 ..... 0010011 @sh
  145. -rori 01100. ........... 101 ..... 0010011 @sh
  146. -grevi 01101. ........... 101 ..... 0010011 @sh
  147. -gorci 00101. ........... 101 ..... 0010011 @sh
  148. +fsl .....10 .......... 001 ..... 0110011 @r3
  149. +fsr .....10 .......... 101 ..... 0110011 @r3
  150. +
  151. +fsri .....1 ........... 101 ..... 0010011 @r3_imm
  152. +bseti 001010 ........... 001 ..... 0010011 @sh6
  153. +bclri 010010 ........... 001 ..... 0010011 @sh6
  154. +binvi 011010 ........... 001 ..... 0010011 @sh6
  155. +bexti 010010 ........... 101 ..... 0010011 @sh6
  156. +sloi 001000 ........... 001 ..... 0010011 @sh6
  157. +sroi 001000 ........... 101 ..... 0010011 @sh6
  158. +rori 011000 ........... 101 ..... 0010011 @sh6
  159. +grevi 011010 ........... 101 ..... 0010011 @sh6
  160. +gorci 001010 ........... 101 ..... 0010011 @sh6
  161. # *** RV64B Standard Extension (in addition to RV32B) ***
  162. clzw 0110000 00000 ..... 001 ..... 0011011 @r2
  163. @@ -728,7 +736,10 @@ sh1add_uw 0010000 .......... 010 ..... 0111011 @r
  164. sh2add_uw 0010000 .......... 100 ..... 0111011 @r
  165. sh3add_uw 0010000 .......... 110 ..... 0111011 @r
  166. add_uw 0000100 .......... 000 ..... 0111011 @r
  167. +fslw .....10 .......... 001 ..... 0111011 @r3
  168. +fsrw .....10 .......... 101 ..... 0111011 @r3
  169. +fsriw .....10 .......... 101 ..... 0011011 @r3w_imm
  170. bsetiw 0010100 .......... 001 ..... 0011011 @sh5
  171. bclriw 0100100 .......... 001 ..... 0011011 @sh5
  172. binviw 0110100 .......... 001 ..... 0011011 @sh5
  173. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  174. index 2a143d9d8f..91762aace5 100644
  175. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  176. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  177. @@ -260,6 +260,55 @@ static bool trans_cmov(DisasContext *ctx, arg_cmov *a)
  178. return gen_quat(ctx, a, gen_helper_cmov);
  179. }
  180. +static bool trans_fsl(DisasContext *ctx, arg_fsl *a)
  181. +{
  182. + REQUIRE_EXT(ctx, RVB);
  183. + return gen_quat(ctx, a, gen_helper_fsl);
  184. +}
  185. +
  186. +static bool trans_fsr(DisasContext *ctx, arg_fsr *a)
  187. +{
  188. + REQUIRE_EXT(ctx, RVB);
  189. + return gen_quat(ctx, a, gen_helper_fsr);
  190. +}
  191. +
  192. +static bool trans_fsri(DisasContext *ctx, arg_fsri *a)
  193. +{
  194. + REQUIRE_EXT(ctx, RVB);
  195. +
  196. + if (a->imm >= 64) {
  197. + return false;
  198. + }
  199. +
  200. + return gen_quati(ctx, a, gen_helper_fsr);
  201. +}
  202. +
  203. +static bool trans_fslw(DisasContext *ctx, arg_fslw *a)
  204. +{
  205. + REQUIRE_64BIT(ctx);
  206. + REQUIRE_EXT(ctx, RVB);
  207. + return gen_quat(ctx, a, gen_helper_fsl);
  208. +}
  209. +
  210. +static bool trans_fsrw(DisasContext *ctx, arg_fsrw *a)
  211. +{
  212. + REQUIRE_64BIT(ctx);
  213. + REQUIRE_EXT(ctx, RVB);
  214. + return gen_quat(ctx, a, gen_helper_fsrw);
  215. +}
  216. +
  217. +static bool trans_fsriw(DisasContext *ctx, arg_fsri *a)
  218. +{
  219. + REQUIRE_64BIT(ctx);
  220. + REQUIRE_EXT(ctx, RVB);
  221. +
  222. + if (a->imm >= 32) {
  223. + return false;
  224. + }
  225. +
  226. + return gen_quati(ctx, a, gen_helper_fsrw);
  227. +}
  228. +
  229. static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
  230. {
  231. REQUIRE_64BIT(ctx);
  232. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  233. index 50aeb2b4c8..daaffa2b26 100644
  234. --- a/target/riscv/translate.c
  235. +++ b/target/riscv/translate.c
  236. @@ -836,6 +836,27 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
  237. return true;
  238. }
  239. +static bool gen_quati(DisasContext *ctx, arg_r3i *a,
  240. + void(*func)(TCGv, TCGv, TCGv, TCGv))
  241. +{
  242. + TCGv source1, source2, source3;
  243. + source1 = tcg_temp_new();
  244. + source2 = tcg_temp_new();
  245. + source3 = tcg_temp_new();
  246. +
  247. + gen_get_gpr(source1, a->rs1);
  248. + tcg_gen_movi_tl(source2, a->imm);
  249. + gen_get_gpr(source3, a->rs3);
  250. +
  251. + (*func)(source1, source1, source2, source3);
  252. +
  253. + gen_set_gpr(a->rd, source1);
  254. + tcg_temp_free(source1);
  255. + tcg_temp_free(source2);
  256. + tcg_temp_free(source3);
  257. + return true;
  258. +}
  259. +
  260. static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
  261. {
  262. DisasContext *ctx = container_of(dcbase, DisasContext, base);
  263. --
  264. 2.33.0