0002-target-riscv-rvb-add-cmix-cmov-instruction.patch 4.7 KB

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  1. From 9401079bda6803c2b7c6251eb579fca5657991d1 Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Thu, 8 Jul 2021 13:43:50 +0800
  4. Subject: [PATCH 02/11] target/riscv: rvb: add cmix/cmov instruction
  5. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  6. ---
  7. target/riscv/bitmanip_helper.c | 12 ++++++++++
  8. target/riscv/helper.h | 1 +
  9. target/riscv/insn32.decode | 5 ++++-
  10. target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++
  11. target/riscv/translate.c | 29 +++++++++++++++++++++++++
  12. 5 files changed, 58 insertions(+), 1 deletion(-)
  13. diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
  14. index 29dfe921ab..46b51399f2 100644
  15. --- a/target/riscv/bitmanip_helper.c
  16. +++ b/target/riscv/bitmanip_helper.c
  17. @@ -122,3 +122,15 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
  18. {
  19. return do_clmulr(rs1, rs2, TARGET_LONG_BITS);
  20. }
  21. +
  22. +static target_ulong do_cmov(target_ulong rs1,
  23. + target_ulong rs2,
  24. + target_ulong rs3)
  25. +{
  26. + return rs2 ? rs1 : rs3;
  27. +}
  28. +
  29. +target_ulong HELPER(cmov)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
  30. +{
  31. + return do_cmov(rs1, rs2, rs3);
  32. +}
  33. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  34. index 6ee9e8d058..1282aada80 100644
  35. --- a/target/riscv/helper.h
  36. +++ b/target/riscv/helper.h
  37. @@ -66,6 +66,7 @@ DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  38. DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  39. DEF_HELPER_FLAGS_2(clmulh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  40. DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  41. +DEF_HELPER_FLAGS_3(cmov, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  42. /* Special functions */
  43. DEF_HELPER_3(csrrw, tl, env, tl, tl)
  44. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  45. index 617ead6669..06527db5f2 100644
  46. --- a/target/riscv/insn32.decode
  47. +++ b/target/riscv/insn32.decode
  48. @@ -42,6 +42,7 @@
  49. &j imm rd
  50. &r rd rs1 rs2
  51. &r2 rd rs1
  52. +&r3 rd rs1 rs2 rs3
  53. &s imm rs1 rs2
  54. &u imm rd
  55. &shift shamt rs1 rd
  56. @@ -66,6 +67,7 @@
  57. @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
  58. @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
  59. +@r3 ..... .. ..... ..... ... ..... ....... &r3 %rs3 %rs2 %rs1 %rd
  60. @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
  61. @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
  62. @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
  63. @@ -692,7 +694,8 @@ sh3add 0010000 .......... 110 ..... 0110011 @r
  64. clmul 0000101 .......... 001 ..... 0110011 @r
  65. clmulh 0000101 .......... 011 ..... 0110011 @r
  66. clmulr 0000101 .......... 010 ..... 0110011 @r
  67. -
  68. +cmix .....11 .......... 001 ..... 0110011 @r3
  69. +cmov .....11 .......... 101 ..... 0110011 @r3
  70. bseti 00101. ........... 001 ..... 0010011 @sh
  71. bclri 01001. ........... 001 ..... 0010011 @sh
  72. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  73. index 181cbf285c..2a143d9d8f 100644
  74. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  75. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  76. @@ -248,6 +248,18 @@ GEN_TRANS_CLMUL(clmul)
  77. GEN_TRANS_CLMUL(clmulh)
  78. GEN_TRANS_CLMUL(clmulr)
  79. +static bool trans_cmix(DisasContext *ctx, arg_cmix *a)
  80. +{
  81. + REQUIRE_EXT(ctx, RVB);
  82. + return gen_quat(ctx, a, gen_cmix);
  83. +}
  84. +
  85. +static bool trans_cmov(DisasContext *ctx, arg_cmov *a)
  86. +{
  87. + REQUIRE_EXT(ctx, RVB);
  88. + return gen_quat(ctx, a, gen_helper_cmov);
  89. +}
  90. +
  91. static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
  92. {
  93. REQUIRE_64BIT(ctx);
  94. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  95. index 62a7d7e4c7..50aeb2b4c8 100644
  96. --- a/target/riscv/translate.c
  97. +++ b/target/riscv/translate.c
  98. @@ -789,6 +789,35 @@ static bool gen_arith(DisasContext *ctx, arg_r *a,
  99. return true;
  100. }
  101. +static void gen_cmix(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3)
  102. +{
  103. + tcg_gen_and_tl(arg1, arg1, arg2);
  104. + tcg_gen_not_tl(arg2, arg2);
  105. + tcg_gen_and_tl(arg3, arg3, arg2);
  106. + tcg_gen_or_tl(ret, arg1, arg3);
  107. +}
  108. +
  109. +static bool gen_quat(DisasContext *ctx, arg_r3 *a,
  110. + void(*func)(TCGv, TCGv, TCGv, TCGv))
  111. +{
  112. + TCGv source1, source2, source3;
  113. + source1 = tcg_temp_new();
  114. + source2 = tcg_temp_new();
  115. + source3 = tcg_temp_new();
  116. +
  117. + gen_get_gpr(source1, a->rs1);
  118. + gen_get_gpr(source2, a->rs2);
  119. + gen_get_gpr(source3, a->rs3);
  120. +
  121. + (*func)(source1, source1, source2, source3);
  122. +
  123. + gen_set_gpr(a->rd, source1);
  124. + tcg_temp_free(source1);
  125. + tcg_temp_free(source2);
  126. + tcg_temp_free(source3);
  127. + return true;
  128. +}
  129. +
  130. static bool gen_shift(DisasContext *ctx, arg_r *a,
  131. void(*func)(TCGv, TCGv, TCGv))
  132. {
  133. --
  134. 2.33.0