0001-target-riscv-rvb-Carry-less-multiply-instruction.patch 4.3 KB

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  1. From 5e47b23aded34646d4a2d0424d5ccc3eff3bcb6c Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Wed, 7 Jul 2021 11:19:22 +0800
  4. Subject: [PATCH 01/11] target/riscv: rvb: Carry-less multiply instruction
  5. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  6. ---
  7. target/riscv/bitmanip_helper.c | 34 +++++++++++++++++++++++++
  8. target/riscv/helper.h | 3 +++
  9. target/riscv/insn32.decode | 4 +++
  10. target/riscv/insn_trans/trans_rvb.c.inc | 11 ++++++++
  11. 4 files changed, 52 insertions(+)
  12. diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
  13. index 5b2f795d03..29dfe921ab 100644
  14. --- a/target/riscv/bitmanip_helper.c
  15. +++ b/target/riscv/bitmanip_helper.c
  16. @@ -88,3 +88,37 @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
  17. {
  18. return do_gorc(rs1, rs2, 32);
  19. }
  20. +
  21. +#define DO_CLMULA(NAME, NUM, BODY) \
  22. +static target_ulong do_##NAME(target_ulong rs1, \
  23. + target_ulong rs2, \
  24. + int bits) \
  25. +{ \
  26. + target_ulong x = 0; \
  27. + int i; \
  28. + \
  29. + for(i = NUM; i < bits; i++) \
  30. + if ((rs2 >> i) & 1) \
  31. + x ^= BODY; \
  32. + \
  33. + return x; \
  34. +}
  35. +
  36. +DO_CLMULA(clmul, 0, (rs1 << i))
  37. +DO_CLMULA(clmulh, 1, (rs1 >> (bits - i)))
  38. +DO_CLMULA(clmulr, 0, (rs1 >> (bits - i - 1)))
  39. +
  40. +target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
  41. +{
  42. + return do_clmul(rs1, rs2, TARGET_LONG_BITS);
  43. +}
  44. +
  45. +target_ulong HELPER(clmulh)(target_ulong rs1, target_ulong rs2)
  46. +{
  47. + return do_clmulh(rs1, rs2, TARGET_LONG_BITS);
  48. +}
  49. +
  50. +target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
  51. +{
  52. + return do_clmulr(rs1, rs2, TARGET_LONG_BITS);
  53. +}
  54. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  55. index 415e37bc37..6ee9e8d058 100644
  56. --- a/target/riscv/helper.h
  57. +++ b/target/riscv/helper.h
  58. @@ -63,6 +63,9 @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  59. DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  60. DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  61. DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  62. +DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  63. +DEF_HELPER_FLAGS_2(clmulh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  64. +DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  65. /* Special functions */
  66. DEF_HELPER_3(csrrw, tl, env, tl, tl)
  67. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  68. index f09f8d5faf..617ead6669 100644
  69. --- a/target/riscv/insn32.decode
  70. +++ b/target/riscv/insn32.decode
  71. @@ -689,6 +689,10 @@ gorc 0010100 .......... 101 ..... 0110011 @r
  72. sh1add 0010000 .......... 010 ..... 0110011 @r
  73. sh2add 0010000 .......... 100 ..... 0110011 @r
  74. sh3add 0010000 .......... 110 ..... 0110011 @r
  75. +clmul 0000101 .......... 001 ..... 0110011 @r
  76. +clmulh 0000101 .......... 011 ..... 0110011 @r
  77. +clmulr 0000101 .......... 010 ..... 0110011 @r
  78. +
  79. bseti 00101. ........... 001 ..... 0010011 @sh
  80. bclri 01001. ........... 001 ..... 0010011 @sh
  81. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  82. index 9e81f6e3de..181cbf285c 100644
  83. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  84. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  85. @@ -237,6 +237,17 @@ GEN_TRANS_SHADD(1)
  86. GEN_TRANS_SHADD(2)
  87. GEN_TRANS_SHADD(3)
  88. +#define GEN_TRANS_CLMUL(NAME) \
  89. +static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
  90. +{ \
  91. + REQUIRE_EXT(ctx, RVB); \
  92. + return gen_arith(ctx, a, gen_helper_##NAME); \
  93. +}
  94. +
  95. +GEN_TRANS_CLMUL(clmul)
  96. +GEN_TRANS_CLMUL(clmulh)
  97. +GEN_TRANS_CLMUL(clmulr)
  98. +
  99. static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
  100. {
  101. REQUIRE_64BIT(ctx);
  102. --
  103. 2.33.0