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- From 5ba304e191c401c8b484c754d2d33b43667243d1 Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Fri, 26 Feb 2021 08:42:17 +0800
- Subject: [PATCH 081/107] target/riscv: rvv-1.0: add vsetivli instruction
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- ---
- target/riscv/insn32.decode | 2 ++
- target/riscv/insn_trans/trans_rvv.c.inc | 30 +++++++++++++++++++++++++
- 2 files changed, 32 insertions(+)
- diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
- index bab4259d91..f6eec02d55 100644
- --- a/target/riscv/insn32.decode
- +++ b/target/riscv/insn32.decode
- @@ -78,6 +78,7 @@
- @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
- @r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
- @r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
- +@r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd
- @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
-
- @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
- @@ -647,6 +648,7 @@ vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
- vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
-
- vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
- +vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10
- vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
-
- # *** RV32Zfh Extension ***
- diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
- index f916f5d064..49f2eeee47 100644
- --- a/target/riscv/insn_trans/trans_rvv.c.inc
- +++ b/target/riscv/insn_trans/trans_rvv.c.inc
- @@ -159,6 +159,29 @@ static bool do_vsetvl(DisasContext *ctx, int rd, int rs1, TCGv s2)
- return true;
- }
-
- +static bool do_vsetivli(DisasContext *ctx, int rd, TCGv s1, TCGv s2)
- +{
- + TCGv dst;
- +
- + if (!require_rvv(ctx) || !has_ext(ctx, RVV)) {
- + return false;
- + }
- +
- + dst = tcg_temp_new();
- +
- + gen_helper_vsetvl(dst, cpu_env, s1, s2);
- + gen_set_gpr(rd, dst);
- + mark_vs_dirty(ctx);
- + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- + lookup_and_goto_ptr(ctx);
- + ctx->base.is_jmp = DISAS_NORETURN;
- +
- + tcg_temp_free(s1);
- + tcg_temp_free(s2);
- + tcg_temp_free(dst);
- + return true;
- +}
- +
- static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
- {
- TCGv s2 = tcg_temp_new();
- @@ -172,6 +195,13 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
- return do_vsetvl(ctx, a->rd, a->rs1, s2);
- }
-
- +static bool trans_vsetivli(DisasContext *ctx, arg_vsetivli *a)
- +{
- + TCGv s1 = tcg_const_tl(a->rs1);
- + TCGv s2 = tcg_const_tl(a->zimm);
- + return do_vsetivli(ctx, a->rd, s1, s2);
- +}
- +
- /* vector register offset from env */
- static uint32_t vreg_ofs(DisasContext *s, int reg)
- {
- --
- 2.33.1
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