0081-target-riscv-rvv-1.0-add-vsetivli-instruction.patch 2.7 KB

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  1. From 5ba304e191c401c8b484c754d2d33b43667243d1 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Fri, 26 Feb 2021 08:42:17 +0800
  4. Subject: [PATCH 081/107] target/riscv: rvv-1.0: add vsetivli instruction
  5. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  6. ---
  7. target/riscv/insn32.decode | 2 ++
  8. target/riscv/insn_trans/trans_rvv.c.inc | 30 +++++++++++++++++++++++++
  9. 2 files changed, 32 insertions(+)
  10. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  11. index bab4259d91..f6eec02d55 100644
  12. --- a/target/riscv/insn32.decode
  13. +++ b/target/riscv/insn32.decode
  14. @@ -78,6 +78,7 @@
  15. @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
  16. @r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
  17. @r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
  18. +@r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd
  19. @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
  20. @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
  21. @@ -647,6 +648,7 @@ vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
  22. vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
  23. vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
  24. +vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10
  25. vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
  26. # *** RV32Zfh Extension ***
  27. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  28. index f916f5d064..49f2eeee47 100644
  29. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  30. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  31. @@ -159,6 +159,29 @@ static bool do_vsetvl(DisasContext *ctx, int rd, int rs1, TCGv s2)
  32. return true;
  33. }
  34. +static bool do_vsetivli(DisasContext *ctx, int rd, TCGv s1, TCGv s2)
  35. +{
  36. + TCGv dst;
  37. +
  38. + if (!require_rvv(ctx) || !has_ext(ctx, RVV)) {
  39. + return false;
  40. + }
  41. +
  42. + dst = tcg_temp_new();
  43. +
  44. + gen_helper_vsetvl(dst, cpu_env, s1, s2);
  45. + gen_set_gpr(rd, dst);
  46. + mark_vs_dirty(ctx);
  47. + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
  48. + lookup_and_goto_ptr(ctx);
  49. + ctx->base.is_jmp = DISAS_NORETURN;
  50. +
  51. + tcg_temp_free(s1);
  52. + tcg_temp_free(s2);
  53. + tcg_temp_free(dst);
  54. + return true;
  55. +}
  56. +
  57. static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
  58. {
  59. TCGv s2 = tcg_temp_new();
  60. @@ -172,6 +195,13 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
  61. return do_vsetvl(ctx, a->rd, a->rs1, s2);
  62. }
  63. +static bool trans_vsetivli(DisasContext *ctx, arg_vsetivli *a)
  64. +{
  65. + TCGv s1 = tcg_const_tl(a->rs1);
  66. + TCGv s2 = tcg_const_tl(a->zimm);
  67. + return do_vsetivli(ctx, a->rd, s1, s2);
  68. +}
  69. +
  70. /* vector register offset from env */
  71. static uint32_t vreg_ofs(DisasContext *s, int reg)
  72. {
  73. --
  74. 2.33.1