0080-target-riscv-rvv-1.0-rename-r2_zimm-to-r2_zimm11.patch 1.6 KB

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  1. From 41f16e8fd38d6c633f53e959f58f825bc4a62a7d Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Fri, 26 Feb 2021 08:42:04 +0800
  4. Subject: [PATCH 080/107] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
  5. Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction.
  6. vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm.
  7. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  8. ---
  9. target/riscv/insn32.decode | 4 ++--
  10. 1 file changed, 2 insertions(+), 2 deletions(-)
  11. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  12. index c90d347af4..bab4259d91 100644
  13. --- a/target/riscv/insn32.decode
  14. +++ b/target/riscv/insn32.decode
  15. @@ -77,7 +77,7 @@
  16. @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
  17. @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
  18. @r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
  19. -@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
  20. +@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
  21. @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
  22. @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
  23. @@ -646,7 +646,7 @@ vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
  24. vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
  25. vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
  26. -vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
  27. +vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
  28. vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
  29. # *** RV32Zfh Extension ***
  30. --
  31. 2.33.1