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- From fb2ee51ba0046703085c961fc029bf93f593a5a9 Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Tue, 6 Oct 2020 23:47:28 +0800
- Subject: [PATCH 079/107] target/riscv: set mstatus.SD bit when writing fp CSRs
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- ---
- target/riscv/csr.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
- diff --git a/target/riscv/csr.c b/target/riscv/csr.c
- index 900c2fa50a..cb3816b124 100644
- --- a/target/riscv/csr.c
- +++ b/target/riscv/csr.c
- @@ -209,7 +209,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -RISCV_EXCP_ILLEGAL_INST;
- }
- - env->mstatus |= MSTATUS_FS;
- + env->mstatus |= MSTATUS_FS | MSTATUS_SD;
- #endif
- riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
- return 0;
- @@ -232,7 +232,7 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -RISCV_EXCP_ILLEGAL_INST;
- }
- - env->mstatus |= MSTATUS_FS;
- + env->mstatus |= MSTATUS_FS | MSTATUS_SD;
- #endif
- env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
- return 0;
- @@ -256,7 +256,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -RISCV_EXCP_ILLEGAL_INST;
- }
- - env->mstatus |= MSTATUS_FS;
- + env->mstatus |= MSTATUS_FS | MSTATUS_SD;
- #endif
- env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
- riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
- --
- 2.33.1
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