0079-target-riscv-set-mstatus.SD-bit-when-writing-fp-CSRs.patch 1.6 KB

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  1. From fb2ee51ba0046703085c961fc029bf93f593a5a9 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Tue, 6 Oct 2020 23:47:28 +0800
  4. Subject: [PATCH 079/107] target/riscv: set mstatus.SD bit when writing fp CSRs
  5. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  6. ---
  7. target/riscv/csr.c | 6 +++---
  8. 1 file changed, 3 insertions(+), 3 deletions(-)
  9. diff --git a/target/riscv/csr.c b/target/riscv/csr.c
  10. index 900c2fa50a..cb3816b124 100644
  11. --- a/target/riscv/csr.c
  12. +++ b/target/riscv/csr.c
  13. @@ -209,7 +209,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
  14. if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
  15. return -RISCV_EXCP_ILLEGAL_INST;
  16. }
  17. - env->mstatus |= MSTATUS_FS;
  18. + env->mstatus |= MSTATUS_FS | MSTATUS_SD;
  19. #endif
  20. riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
  21. return 0;
  22. @@ -232,7 +232,7 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
  23. if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
  24. return -RISCV_EXCP_ILLEGAL_INST;
  25. }
  26. - env->mstatus |= MSTATUS_FS;
  27. + env->mstatus |= MSTATUS_FS | MSTATUS_SD;
  28. #endif
  29. env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
  30. return 0;
  31. @@ -256,7 +256,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
  32. if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
  33. return -RISCV_EXCP_ILLEGAL_INST;
  34. }
  35. - env->mstatus |= MSTATUS_FS;
  36. + env->mstatus |= MSTATUS_FS | MSTATUS_SD;
  37. #endif
  38. env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
  39. riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
  40. --
  41. 2.33.1