0077-target-riscv-rvv-1.0-floating-point-reciprocal-squar.patch 8.9 KB

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  1. From 56caeae679dde82a2da2536758dabd58e2d0becf Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 19 Nov 2020 14:36:04 +0800
  4. Subject: [PATCH 077/107] target/riscv: rvv-1.0: floating-point reciprocal
  5. square-root estimate instruction
  6. Implement the floating-point reciprocal square-root estimate to 7 bits
  7. instruction.
  8. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  9. ---
  10. target/riscv/helper.h | 4 +
  11. target/riscv/insn32.decode | 1 +
  12. target/riscv/insn_trans/trans_rvv.c.inc | 1 +
  13. target/riscv/vector_helper.c | 183 ++++++++++++++++++++++++
  14. 4 files changed, 189 insertions(+)
  15. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  16. index e233548623..807d1f7202 100644
  17. --- a/target/riscv/helper.h
  18. +++ b/target/riscv/helper.h
  19. @@ -916,6 +916,10 @@ DEF_HELPER_5(vfsqrt_v_h, void, ptr, ptr, ptr, env, i32)
  20. DEF_HELPER_5(vfsqrt_v_w, void, ptr, ptr, ptr, env, i32)
  21. DEF_HELPER_5(vfsqrt_v_d, void, ptr, ptr, ptr, env, i32)
  22. +DEF_HELPER_5(vfrsqrt7_v_h, void, ptr, ptr, ptr, env, i32)
  23. +DEF_HELPER_5(vfrsqrt7_v_w, void, ptr, ptr, ptr, env, i32)
  24. +DEF_HELPER_5(vfrsqrt7_v_d, void, ptr, ptr, ptr, env, i32)
  25. +
  26. DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  27. DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  28. DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
  29. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  30. index 65d84f0b7c..0c7fd17d56 100644
  31. --- a/target/riscv/insn32.decode
  32. +++ b/target/riscv/insn32.decode
  33. @@ -535,6 +535,7 @@ vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
  34. vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
  35. vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
  36. vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
  37. +vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm
  38. vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
  39. vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
  40. vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
  41. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  42. index f032a596b5..a53f0158ee 100644
  43. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  44. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  45. @@ -2638,6 +2638,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  46. }
  47. GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN)
  48. +GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN)
  49. /* Vector Floating-Point MIN/MAX Instructions */
  50. GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
  51. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  52. index 7a2d2e7949..7d8f05ae21 100644
  53. --- a/target/riscv/vector_helper.c
  54. +++ b/target/riscv/vector_helper.c
  55. @@ -18,6 +18,7 @@
  56. #include "qemu/osdep.h"
  57. #include "qemu/host-utils.h"
  58. +#include "qemu/bitops.h"
  59. #include "cpu.h"
  60. #include "exec/memop.h"
  61. #include "exec/exec-all.h"
  62. @@ -3638,6 +3639,188 @@ GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2)
  63. GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4)
  64. GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8)
  65. +/*
  66. + * Vector Floating-Point Reciprocal Square-Root Estimate Instruction
  67. + *
  68. + * Adapted from riscv-v-spec recip.c:
  69. + * https://github.com/riscv/riscv-v-spec/blob/master/recip.c
  70. + */
  71. +static uint64_t frsqrt7(uint64_t f, int exp_size, int frac_size)
  72. +{
  73. + uint64_t sign = extract64(f, frac_size + exp_size, 1);
  74. + uint64_t exp = extract64(f, frac_size, exp_size);
  75. + uint64_t frac = extract64(f, 0, frac_size);
  76. +
  77. + const uint8_t lookup_table[] = {
  78. + 52, 51, 50, 48, 47, 46, 44, 43,
  79. + 42, 41, 40, 39, 38, 36, 35, 34,
  80. + 33, 32, 31, 30, 30, 29, 28, 27,
  81. + 26, 25, 24, 23, 23, 22, 21, 20,
  82. + 19, 19, 18, 17, 16, 16, 15, 14,
  83. + 14, 13, 12, 12, 11, 10, 10, 9,
  84. + 9, 8, 7, 7, 6, 6, 5, 4,
  85. + 4, 3, 3, 2, 2, 1, 1, 0,
  86. + 127, 125, 123, 121, 119, 118, 116, 114,
  87. + 113, 111, 109, 108, 106, 105, 103, 102,
  88. + 100, 99, 97, 96, 95, 93, 92, 91,
  89. + 90, 88, 87, 86, 85, 84, 83, 82,
  90. + 80, 79, 78, 77, 76, 75, 74, 73,
  91. + 72, 71, 70, 70, 69, 68, 67, 66,
  92. + 65, 64, 63, 63, 62, 61, 60, 59,
  93. + 59, 58, 57, 56, 56, 55, 54, 53
  94. + };
  95. + const int precision = 7;
  96. +
  97. + if (exp == 0 && frac != 0) { /* subnormal */
  98. + /* Normalize the subnormal. */
  99. + while (extract64(frac, frac_size - 1, 1) == 0) {
  100. + exp--;
  101. + frac <<= 1;
  102. + }
  103. +
  104. + frac = (frac << 1) & MAKE_64BIT_MASK(0, frac_size);
  105. + }
  106. +
  107. + int idx = ((exp & 1) << (precision - 1)) |
  108. + (frac >> (frac_size - precision + 1));
  109. + uint64_t out_frac = (uint64_t)(lookup_table[idx]) <<
  110. + (frac_size - precision);
  111. + uint64_t out_exp = (3 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp) / 2;
  112. +
  113. + uint64_t val = 0;
  114. + val = deposit64(val, 0, frac_size, out_frac);
  115. + val = deposit64(val, frac_size, exp_size, out_exp);
  116. + val = deposit64(val, frac_size + exp_size, 1, sign);
  117. + return val;
  118. +}
  119. +
  120. +static float16 frsqrt7_h(float16 f, float_status *s)
  121. +{
  122. + int exp_size = 5, frac_size = 10;
  123. + bool sign = float16_is_neg(f);
  124. +
  125. + /*
  126. + * frsqrt7(sNaN) = canonical NaN
  127. + * frsqrt7(-inf) = canonical NaN
  128. + * frsqrt7(-normal) = canonical NaN
  129. + * frsqrt7(-subnormal) = canonical NaN
  130. + */
  131. + if (float16_is_signaling_nan(f, s) ||
  132. + (float16_is_infinity(f) && sign) ||
  133. + (float16_is_normal(f) && sign) ||
  134. + (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) {
  135. + s->float_exception_flags |= float_flag_invalid;
  136. + return float16_default_nan(s);
  137. + }
  138. +
  139. + /* frsqrt7(qNaN) = canonical NaN */
  140. + if (float16_is_quiet_nan(f, s)) {
  141. + return float16_default_nan(s);
  142. + }
  143. +
  144. + /* frsqrt7(+-0) = +-inf */
  145. + if (float16_is_zero(f)) {
  146. + s->float_exception_flags |= float_flag_divbyzero;
  147. + return float16_set_sign(float16_infinity, sign);
  148. + }
  149. +
  150. + /* frsqrt7(+inf) = +0 */
  151. + if (float16_is_infinity(f) && !sign) {
  152. + return float16_set_sign(float16_zero, sign);
  153. + }
  154. +
  155. + /* +normal, +subnormal */
  156. + uint64_t val = frsqrt7(f, exp_size, frac_size);
  157. + return make_float16(val);
  158. +}
  159. +
  160. +static float32 frsqrt7_s(float32 f, float_status *s)
  161. +{
  162. + int exp_size = 8, frac_size = 23;
  163. + bool sign = float32_is_neg(f);
  164. +
  165. + /*
  166. + * frsqrt7(sNaN) = canonical NaN
  167. + * frsqrt7(-inf) = canonical NaN
  168. + * frsqrt7(-normal) = canonical NaN
  169. + * frsqrt7(-subnormal) = canonical NaN
  170. + */
  171. + if (float32_is_signaling_nan(f, s) ||
  172. + (float32_is_infinity(f) && sign) ||
  173. + (float32_is_normal(f) && sign) ||
  174. + (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) {
  175. + s->float_exception_flags |= float_flag_invalid;
  176. + return float32_default_nan(s);
  177. + }
  178. +
  179. + /* frsqrt7(qNaN) = canonical NaN */
  180. + if (float32_is_quiet_nan(f, s)) {
  181. + return float32_default_nan(s);
  182. + }
  183. +
  184. + /* frsqrt7(+-0) = +-inf */
  185. + if (float32_is_zero(f)) {
  186. + s->float_exception_flags |= float_flag_divbyzero;
  187. + return float32_set_sign(float32_infinity, sign);
  188. + }
  189. +
  190. + /* frsqrt7(+inf) = +0 */
  191. + if (float32_is_infinity(f) && !sign) {
  192. + return float32_set_sign(float32_zero, sign);
  193. + }
  194. +
  195. + /* +normal, +subnormal */
  196. + uint64_t val = frsqrt7(f, exp_size, frac_size);
  197. + return make_float32(val);
  198. +}
  199. +
  200. +static float64 frsqrt7_d(float64 f, float_status *s)
  201. +{
  202. + int exp_size = 11, frac_size = 52;
  203. + bool sign = float64_is_neg(f);
  204. +
  205. + /*
  206. + * frsqrt7(sNaN) = canonical NaN
  207. + * frsqrt7(-inf) = canonical NaN
  208. + * frsqrt7(-normal) = canonical NaN
  209. + * frsqrt7(-subnormal) = canonical NaN
  210. + */
  211. + if (float64_is_signaling_nan(f, s) ||
  212. + (float64_is_infinity(f) && sign) ||
  213. + (float64_is_normal(f) && sign) ||
  214. + (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) {
  215. + s->float_exception_flags |= float_flag_invalid;
  216. + return float64_default_nan(s);
  217. + }
  218. +
  219. + /* frsqrt7(qNaN) = canonical NaN */
  220. + if (float64_is_quiet_nan(f, s)) {
  221. + return float64_default_nan(s);
  222. + }
  223. +
  224. + /* frsqrt7(+-0) = +-inf */
  225. + if (float64_is_zero(f)) {
  226. + s->float_exception_flags |= float_flag_divbyzero;
  227. + return float64_set_sign(float64_infinity, sign);
  228. + }
  229. +
  230. + /* frsqrt7(+inf) = +0 */
  231. + if (float64_is_infinity(f) && !sign) {
  232. + return float64_set_sign(float64_zero, sign);
  233. + }
  234. +
  235. + /* +normal, +subnormal */
  236. + uint64_t val = frsqrt7(f, exp_size, frac_size);
  237. + return make_float64(val);
  238. +}
  239. +
  240. +RVVCALL(OPFVV1, vfrsqrt7_v_h, OP_UU_H, H2, H2, frsqrt7_h)
  241. +RVVCALL(OPFVV1, vfrsqrt7_v_w, OP_UU_W, H4, H4, frsqrt7_s)
  242. +RVVCALL(OPFVV1, vfrsqrt7_v_d, OP_UU_D, H8, H8, frsqrt7_d)
  243. +GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2, 2)
  244. +GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4, 4)
  245. +GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8, 8)
  246. +
  247. /* Vector Floating-Point MIN/MAX Instructions */
  248. RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum_noprop)
  249. RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum_noprop)
  250. --
  251. 2.33.1