0071-target-riscv-rvv-1.0-narrowing-floating-point-intege.patch 12 KB

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  1. From ab9b645b33f23f4e2fef14032c50b9351efd0d70 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Mon, 17 Aug 2020 13:38:30 +0800
  4. Subject: [PATCH 071/107] target/riscv: rvv-1.0: narrowing
  5. floating-point/integer type-convert
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. ---
  8. target/riscv/helper.h | 22 +++++-----
  9. target/riscv/insn32.decode | 15 ++++---
  10. target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++++++++++++++++++----
  11. target/riscv/vector_helper.c | 45 ++++++++++---------
  12. 4 files changed, 96 insertions(+), 44 deletions(-)
  13. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  14. index a2a82e92e5..572d2e5a4c 100644
  15. --- a/target/riscv/helper.h
  16. +++ b/target/riscv/helper.h
  17. @@ -1013,16 +1013,18 @@ DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
  18. DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
  19. DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
  20. -DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
  21. -DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
  22. -DEF_HELPER_5(vfncvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
  23. -DEF_HELPER_5(vfncvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
  24. -DEF_HELPER_5(vfncvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
  25. -DEF_HELPER_5(vfncvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
  26. -DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
  27. -DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
  28. -DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
  29. -DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
  30. +DEF_HELPER_5(vfncvt_xu_f_w_b, void, ptr, ptr, ptr, env, i32)
  31. +DEF_HELPER_5(vfncvt_xu_f_w_h, void, ptr, ptr, ptr, env, i32)
  32. +DEF_HELPER_5(vfncvt_xu_f_w_w, void, ptr, ptr, ptr, env, i32)
  33. +DEF_HELPER_5(vfncvt_x_f_w_b, void, ptr, ptr, ptr, env, i32)
  34. +DEF_HELPER_5(vfncvt_x_f_w_h, void, ptr, ptr, ptr, env, i32)
  35. +DEF_HELPER_5(vfncvt_x_f_w_w, void, ptr, ptr, ptr, env, i32)
  36. +DEF_HELPER_5(vfncvt_f_xu_w_h, void, ptr, ptr, ptr, env, i32)
  37. +DEF_HELPER_5(vfncvt_f_xu_w_w, void, ptr, ptr, ptr, env, i32)
  38. +DEF_HELPER_5(vfncvt_f_x_w_h, void, ptr, ptr, ptr, env, i32)
  39. +DEF_HELPER_5(vfncvt_f_x_w_w, void, ptr, ptr, ptr, env, i32)
  40. +DEF_HELPER_5(vfncvt_f_f_w_h, void, ptr, ptr, ptr, env, i32)
  41. +DEF_HELPER_5(vfncvt_f_f_w_w, void, ptr, ptr, ptr, env, i32)
  42. DEF_HELPER_6(vredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
  43. DEF_HELPER_6(vredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
  44. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  45. index 2d648ffd24..65d84f0b7c 100644
  46. --- a/target/riscv/insn32.decode
  47. +++ b/target/riscv/insn32.decode
  48. @@ -575,11 +575,16 @@ vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
  49. vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
  50. vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
  51. vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
  52. -vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm
  53. -vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm
  54. -vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm
  55. -vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm
  56. -vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm
  57. +
  58. +vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm
  59. +vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm
  60. +vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm
  61. +vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm
  62. +vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm
  63. +vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm
  64. +vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm
  65. +vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm
  66. +
  67. vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm
  68. vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm
  69. vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm
  70. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  71. index da8bf8940e..ea79cfe7b8 100644
  72. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  73. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  74. @@ -2853,17 +2853,17 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
  75. vext_check_sd(s, a->rd, a->rs2, a->vm);
  76. }
  77. -#define GEN_OPFV_NARROW_TRANS(NAME) \
  78. +#define GEN_OPFV_NARROW_TRANS(NAME, HELPER, FRM) \
  79. static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  80. { \
  81. if (opfv_narrow_check(s, a)) { \
  82. uint32_t data = 0; \
  83. static gen_helper_gvec_3_ptr * const fns[2] = { \
  84. - gen_helper_##NAME##_h, \
  85. - gen_helper_##NAME##_w, \
  86. + gen_helper_##HELPER##_h, \
  87. + gen_helper_##HELPER##_w, \
  88. }; \
  89. TCGLabel *over = gen_new_label(); \
  90. - gen_set_rm(s, RISCV_FRM_DYN); \
  91. + gen_set_rm(s, FRM); \
  92. tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
  93. \
  94. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  95. @@ -2878,11 +2878,51 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  96. return false; \
  97. }
  98. -GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v)
  99. -GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v)
  100. -GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v)
  101. -GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v)
  102. -GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
  103. +GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, vfncvt_f_xu_w, RISCV_FRM_DYN)
  104. +GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, vfncvt_f_x_w, RISCV_FRM_DYN)
  105. +GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, vfncvt_f_f_w, RISCV_FRM_DYN)
  106. +/* Reuse the helper function from vfncvt.f.f.w */
  107. +GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, vfncvt_f_f_w, RISCV_FRM_ROD)
  108. +
  109. +static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
  110. +{
  111. + return require_rvv(s) &&
  112. + require_scale_rvf(s) &&
  113. + vext_check_isa_ill(s) &&
  114. + /* OPFV narrowing instructions ignore vs1 check */
  115. + vext_check_sd(s, a->rd, a->rs2, a->vm);
  116. +}
  117. +
  118. +#define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM) \
  119. +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  120. +{ \
  121. + if (opxfv_narrow_check(s, a)) { \
  122. + uint32_t data = 0; \
  123. + static gen_helper_gvec_3_ptr * const fns[3] = { \
  124. + gen_helper_##HELPER##_b, \
  125. + gen_helper_##HELPER##_h, \
  126. + gen_helper_##HELPER##_w, \
  127. + }; \
  128. + TCGLabel *over = gen_new_label(); \
  129. + gen_set_rm(s, FRM); \
  130. + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
  131. + \
  132. + data = FIELD_DP32(data, VDATA, VM, a->vm); \
  133. + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  134. + vreg_ofs(s, a->rs2), cpu_env, 0, \
  135. + s->vlen / 8, data, fns[s->sew]); \
  136. + mark_vs_dirty(s); \
  137. + gen_set_label(over); \
  138. + return true; \
  139. + } \
  140. + return false; \
  141. +}
  142. +
  143. +GEN_OPXFV_NARROW_TRANS(vfncvt_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_DYN)
  144. +GEN_OPXFV_NARROW_TRANS(vfncvt_x_f_w, vfncvt_x_f_w, RISCV_FRM_DYN)
  145. +/* Reuse the helper functions from vfncvt.xu.f.w and vfncvt.x.f.w */
  146. +GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_RTZ)
  147. +GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_x_f_w, vfncvt_x_f_w, RISCV_FRM_RTZ)
  148. /*
  149. *** Vector Reduction Operations
  150. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  151. index 6e2995b8ca..91dccdb04d 100644
  152. --- a/target/riscv/vector_helper.c
  153. +++ b/target/riscv/vector_helper.c
  154. @@ -4029,31 +4029,36 @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8)
  155. /* Narrowing Floating-Point/Integer Type-Convert Instructions */
  156. /* (TD, T2, TX2) */
  157. +#define NOP_UU_B uint8_t, uint16_t, uint32_t
  158. #define NOP_UU_H uint16_t, uint32_t, uint32_t
  159. #define NOP_UU_W uint32_t, uint64_t, uint64_t
  160. /* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
  161. -RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16)
  162. -RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32)
  163. -GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2)
  164. -GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4)
  165. +RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8)
  166. +RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16)
  167. +RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32)
  168. +GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1, 1)
  169. +GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2, 2)
  170. +GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4, 4)
  171. /* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */
  172. -RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16)
  173. -RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32)
  174. -GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2)
  175. -GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4)
  176. +RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8)
  177. +RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16)
  178. +RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32)
  179. +GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1, 1)
  180. +GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2, 2)
  181. +GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4, 4)
  182. /* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
  183. -RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16)
  184. -RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32)
  185. -GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2)
  186. -GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4)
  187. +RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16)
  188. +RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32)
  189. +GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2, 2)
  190. +GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4, 4)
  191. /* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */
  192. -RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16)
  193. -RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32)
  194. -GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2)
  195. -GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4)
  196. +RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16)
  197. +RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32)
  198. +GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2, 2)
  199. +GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4, 4)
  200. /* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */
  201. static uint16_t vfncvtffv16(uint32_t a, float_status *s)
  202. @@ -4061,10 +4066,10 @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s)
  203. return float32_to_float16(a, true, s);
  204. }
  205. -RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16)
  206. -RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32)
  207. -GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2)
  208. -GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4)
  209. +RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16)
  210. +RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32)
  211. +GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2, 2)
  212. +GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4, 4)
  213. /*
  214. *** Vector Reduction Operations
  215. --
  216. 2.33.1