0069-target-riscv-rvv-1.0-widening-floating-point-integer.patch 9.2 KB

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  1. From e5d64e4ca124cce1c3f91bef3048dc169548163d Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Mon, 17 Aug 2020 14:52:27 +0800
  4. Subject: [PATCH 069/107] target/riscv: rvv-1.0: widening
  5. floating-point/integer type-convert
  6. Add the following instructions:
  7. * vfwcvt.rtz.xu.f.v
  8. * vfwcvt.rtz.x.f.v
  9. Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point
  10. rounding modes.
  11. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  12. ---
  13. target/riscv/helper.h | 2 +
  14. target/riscv/insn32.decode | 13 +++---
  15. target/riscv/insn_trans/trans_rvv.c.inc | 54 +++++++++++++++++++++----
  16. target/riscv/vector_helper.c | 7 +++-
  17. 4 files changed, 62 insertions(+), 14 deletions(-)
  18. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  19. index 1ad2df98ff..51174cdafa 100644
  20. --- a/target/riscv/helper.h
  21. +++ b/target/riscv/helper.h
  22. @@ -1003,8 +1003,10 @@ DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
  23. DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
  24. DEF_HELPER_5(vfwcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
  25. DEF_HELPER_5(vfwcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
  26. +DEF_HELPER_5(vfwcvt_f_xu_v_b, void, ptr, ptr, ptr, env, i32)
  27. DEF_HELPER_5(vfwcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
  28. DEF_HELPER_5(vfwcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
  29. +DEF_HELPER_5(vfwcvt_f_x_v_b, void, ptr, ptr, ptr, env, i32)
  30. DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
  31. DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
  32. DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
  33. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  34. index c3482a5f44..2d648ffd24 100644
  35. --- a/target/riscv/insn32.decode
  36. +++ b/target/riscv/insn32.decode
  37. @@ -567,11 +567,14 @@ vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
  38. vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
  39. vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
  40. vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
  41. -vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm
  42. -vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm
  43. -vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm
  44. -vfwcvt_f_x_v 100010 . ..... 01011 001 ..... 1010111 @r2_vm
  45. -vfwcvt_f_f_v 100010 . ..... 01100 001 ..... 1010111 @r2_vm
  46. +
  47. +vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm
  48. +vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm
  49. +vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm
  50. +vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
  51. +vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
  52. +vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
  53. +vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
  54. vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm
  55. vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm
  56. vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm
  57. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  58. index 86eefbf87b..da8bf8940e 100644
  59. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  60. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  61. @@ -2768,12 +2768,54 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
  62. vext_check_ds(s, a->rd, a->rs2, a->vm);
  63. }
  64. -#define GEN_OPFV_WIDEN_TRANS(NAME) \
  65. +#define GEN_OPFV_WIDEN_TRANS(NAME, HELPER, FRM) \
  66. static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  67. { \
  68. if (opfv_widen_check(s, a)) { \
  69. uint32_t data = 0; \
  70. static gen_helper_gvec_3_ptr * const fns[2] = { \
  71. + gen_helper_##HELPER##_h, \
  72. + gen_helper_##HELPER##_w, \
  73. + }; \
  74. + TCGLabel *over = gen_new_label(); \
  75. + gen_set_rm(s, FRM); \
  76. + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
  77. + \
  78. + data = FIELD_DP32(data, VDATA, VM, a->vm); \
  79. + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  80. + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  81. + vreg_ofs(s, a->rs2), cpu_env, 0, \
  82. + s->vlen / 8, data, fns[s->sew - 1]); \
  83. + mark_vs_dirty(s); \
  84. + gen_set_label(over); \
  85. + return true; \
  86. + } \
  87. + return false; \
  88. +}
  89. +
  90. +GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v, vfwcvt_xu_f_v, RISCV_FRM_DYN)
  91. +GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v, vfwcvt_x_f_v, RISCV_FRM_DYN)
  92. +GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v, vfwcvt_f_f_v, RISCV_FRM_DYN)
  93. +/* Reuse the helper functions from vfwcvt.xu.f.v and vfwcvt.x.f.v */
  94. +GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_xu_f_v, vfwcvt_xu_f_v, RISCV_FRM_RTZ)
  95. +GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_x_f_v, vfwcvt_x_f_v, RISCV_FRM_RTZ)
  96. +
  97. +static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
  98. +{
  99. + return require_rvv(s) &&
  100. + require_scale_rvf(s) &&
  101. + vext_check_isa_ill(s) &&
  102. + /* OPFV widening instructions ignore vs1 check */
  103. + vext_check_ds(s, a->rd, a->rs2, a->vm);
  104. +}
  105. +
  106. +#define GEN_OPFXV_WIDEN_TRANS(NAME) \
  107. +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  108. +{ \
  109. + if (opfxv_widen_check(s, a)) { \
  110. + uint32_t data = 0; \
  111. + static gen_helper_gvec_3_ptr * const fns[3] = { \
  112. + gen_helper_##NAME##_b, \
  113. gen_helper_##NAME##_h, \
  114. gen_helper_##NAME##_w, \
  115. }; \
  116. @@ -2782,10 +2824,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  117. tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
  118. \
  119. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  120. - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  121. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  122. vreg_ofs(s, a->rs2), cpu_env, 0, \
  123. - s->vlen / 8, data, fns[s->sew - 1]); \
  124. + s->vlen / 8, data, fns[s->sew]); \
  125. mark_vs_dirty(s); \
  126. gen_set_label(over); \
  127. return true; \
  128. @@ -2793,11 +2834,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  129. return false; \
  130. }
  131. -GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v)
  132. -GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v)
  133. -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v)
  134. -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v)
  135. -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
  136. +GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_xu_v)
  137. +GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_x_v)
  138. /* Narrowing Floating-Point/Integer Type-Convert Instructions */
  139. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  140. index 45ad6eaa96..6e2995b8ca 100644
  141. --- a/target/riscv/vector_helper.c
  142. +++ b/target/riscv/vector_helper.c
  143. @@ -3982,6 +3982,7 @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8)
  144. /* Widening Floating-Point/Integer Type-Convert Instructions */
  145. /* (TD, T2, TX2) */
  146. +#define WOP_UU_B uint16_t, uint8_t, uint8_t
  147. #define WOP_UU_H uint32_t, uint16_t, uint16_t
  148. #define WOP_UU_W uint64_t, uint32_t, uint32_t
  149. /* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/
  150. @@ -3997,19 +3998,23 @@ GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4)
  151. GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8)
  152. /* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */
  153. +RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16)
  154. RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
  155. RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
  156. +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 1, 2)
  157. GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4)
  158. GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8)
  159. /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */
  160. +RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16)
  161. RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32)
  162. RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64)
  163. +GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 1, 2)
  164. GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4)
  165. GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8)
  166. /*
  167. - * vfwcvt.f.f.v vd, vs2, vm #
  168. + * vfwcvt.f.f.v vd, vs2, vm
  169. * Convert single-width float to double-width float.
  170. */
  171. static uint32_t vfwcvtffv16(uint16_t a, float_status *s)
  172. --
  173. 2.33.1