0067-target-riscv-introduce-floating-point-rounding-mode-.patch 8.0 KB

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  1. From 70d3125d83a632a33ea81cfe889608cccc31416f Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Wed, 5 Aug 2020 11:08:59 +0800
  4. Subject: [PATCH 067/107] target/riscv: introduce floating-point rounding mode
  5. enum
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/fpu_helper.c | 12 ++++++------
  10. target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++---------
  11. target/riscv/internals.h | 9 +++++++++
  12. 3 files changed, 24 insertions(+), 15 deletions(-)
  13. diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
  14. index 09d37c1384..96d7762243 100644
  15. --- a/target/riscv/fpu_helper.c
  16. +++ b/target/riscv/fpu_helper.c
  17. @@ -55,23 +55,23 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
  18. {
  19. int softrm;
  20. - if (rm == 7) {
  21. + if (rm == RISCV_FRM_DYN) {
  22. rm = env->frm;
  23. }
  24. switch (rm) {
  25. - case 0:
  26. + case RISCV_FRM_RNE:
  27. softrm = float_round_nearest_even;
  28. break;
  29. - case 1:
  30. + case RISCV_FRM_RTZ:
  31. softrm = float_round_to_zero;
  32. break;
  33. - case 2:
  34. + case RISCV_FRM_RDN:
  35. softrm = float_round_down;
  36. break;
  37. - case 3:
  38. + case RISCV_FRM_RUP:
  39. softrm = float_round_up;
  40. break;
  41. - case 4:
  42. + case RISCV_FRM_RMM:
  43. softrm = float_round_ties_away;
  44. break;
  45. default:
  46. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  47. index 8cc79f1228..92f66728c6 100644
  48. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  49. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  50. @@ -2321,7 +2321,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  51. gen_helper_##NAME##_d, \
  52. }; \
  53. TCGLabel *over = gen_new_label(); \
  54. - gen_set_rm(s, 7); \
  55. + gen_set_rm(s, RISCV_FRM_DYN); \
  56. tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
  57. \
  58. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  59. @@ -2400,7 +2400,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  60. gen_helper_##NAME##_w, \
  61. gen_helper_##NAME##_d, \
  62. }; \
  63. - gen_set_rm(s, 7); \
  64. + gen_set_rm(s, RISCV_FRM_DYN); \
  65. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  66. data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  67. return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
  68. @@ -2432,7 +2432,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  69. gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
  70. }; \
  71. TCGLabel *over = gen_new_label(); \
  72. - gen_set_rm(s, 7); \
  73. + gen_set_rm(s, RISCV_FRM_DYN); \
  74. tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
  75. \
  76. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  77. @@ -2468,7 +2468,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  78. static gen_helper_opfvf *const fns[2] = { \
  79. gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
  80. }; \
  81. - gen_set_rm(s, 7); \
  82. + gen_set_rm(s, RISCV_FRM_DYN); \
  83. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  84. data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  85. return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
  86. @@ -2498,7 +2498,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  87. gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
  88. }; \
  89. TCGLabel *over = gen_new_label(); \
  90. - gen_set_rm(s, 7); \
  91. + gen_set_rm(s, RISCV_FRM_DYN); \
  92. tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
  93. \
  94. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  95. @@ -2534,7 +2534,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  96. static gen_helper_opfvf *const fns[2] = { \
  97. gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
  98. }; \
  99. - gen_set_rm(s, 7); \
  100. + gen_set_rm(s, RISCV_FRM_DYN); \
  101. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  102. data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  103. return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
  104. @@ -2611,7 +2611,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  105. gen_helper_##NAME##_d, \
  106. }; \
  107. TCGLabel *over = gen_new_label(); \
  108. - gen_set_rm(s, 7); \
  109. + gen_set_rm(s, RISCV_FRM_DYN); \
  110. tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
  111. \
  112. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  113. @@ -2757,7 +2757,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  114. gen_helper_##NAME##_w, \
  115. }; \
  116. TCGLabel *over = gen_new_label(); \
  117. - gen_set_rm(s, 7); \
  118. + gen_set_rm(s, RISCV_FRM_DYN); \
  119. tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
  120. \
  121. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  122. @@ -2804,7 +2804,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  123. gen_helper_##NAME##_w, \
  124. }; \
  125. TCGLabel *over = gen_new_label(); \
  126. - gen_set_rm(s, 7); \
  127. + gen_set_rm(s, RISCV_FRM_DYN); \
  128. tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
  129. \
  130. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  131. diff --git a/target/riscv/internals.h b/target/riscv/internals.h
  132. index ac062dc0b4..db105d4d64 100644
  133. --- a/target/riscv/internals.h
  134. +++ b/target/riscv/internals.h
  135. @@ -36,6 +36,15 @@ target_ulong fclass_d(uint64_t frs1);
  136. extern const VMStateDescription vmstate_riscv_cpu;
  137. #endif
  138. +enum {
  139. + RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */
  140. + RISCV_FRM_RTZ = 1, /* Round towards Zero */
  141. + RISCV_FRM_RDN = 2, /* Round Down */
  142. + RISCV_FRM_RUP = 3, /* Round Up */
  143. + RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
  144. + RISCV_FRM_DYN = 7, /* Dynamic rounding mode */
  145. +};
  146. +
  147. static inline uint64_t nanbox_s(float32 f)
  148. {
  149. return f | MAKE_64BIT_MASK(32, 32);
  150. --
  151. 2.33.1