0063-target-riscv-rvv-1.0-remove-widening-saturating-scal.patch 11 KB

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  1. From 21fcf80f52cdf536c6196cacaa8048c5d751beaf Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 2 Jul 2020 16:08:39 +0800
  4. Subject: [PATCH 063/107] target/riscv: rvv-1.0: remove widening saturating
  5. scaled multiply-add
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/helper.h | 22 ---
  10. target/riscv/insn32.decode | 7 -
  11. target/riscv/insn_trans/trans_rvv.c.inc | 9 --
  12. target/riscv/vector_helper.c | 205 ------------------------
  13. 4 files changed, 243 deletions(-)
  14. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  15. index 7ba8c77c6f..69b9e687c0 100644
  16. --- a/target/riscv/helper.h
  17. +++ b/target/riscv/helper.h
  18. @@ -761,28 +761,6 @@ DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  19. DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  20. DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32)
  21. -DEF_HELPER_6(vwsmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  22. -DEF_HELPER_6(vwsmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  23. -DEF_HELPER_6(vwsmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  24. -DEF_HELPER_6(vwsmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  25. -DEF_HELPER_6(vwsmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  26. -DEF_HELPER_6(vwsmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  27. -DEF_HELPER_6(vwsmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  28. -DEF_HELPER_6(vwsmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  29. -DEF_HELPER_6(vwsmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  30. -DEF_HELPER_6(vwsmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
  31. -DEF_HELPER_6(vwsmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  32. -DEF_HELPER_6(vwsmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  33. -DEF_HELPER_6(vwsmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32)
  34. -DEF_HELPER_6(vwsmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  35. -DEF_HELPER_6(vwsmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  36. -DEF_HELPER_6(vwsmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
  37. -DEF_HELPER_6(vwsmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  38. -DEF_HELPER_6(vwsmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  39. -DEF_HELPER_6(vwsmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
  40. -DEF_HELPER_6(vwsmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  41. -DEF_HELPER_6(vwsmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  42. -
  43. DEF_HELPER_6(vssrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  44. DEF_HELPER_6(vssrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  45. DEF_HELPER_6(vssrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  46. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  47. index 302b687a2d..11dece1383 100644
  48. --- a/target/riscv/insn32.decode
  49. +++ b/target/riscv/insn32.decode
  50. @@ -478,13 +478,6 @@ vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
  51. vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
  52. vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
  53. vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
  54. -vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm
  55. -vwsmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm
  56. -vwsmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm
  57. -vwsmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm
  58. -vwsmaccsu_vv 111110 . ..... ..... 000 ..... 1010111 @r_vm
  59. -vwsmaccsu_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm
  60. -vwsmaccus_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm
  61. vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm
  62. vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm
  63. vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
  64. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  65. index 2c601435ce..73676cc030 100644
  66. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  67. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  68. @@ -2249,15 +2249,6 @@ GEN_OPIVX_TRANS(vasubu_vx, opivx_check)
  69. GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
  70. GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
  71. -/* Vector Widening Saturating Scaled Multiply-Add */
  72. -GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check)
  73. -GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check)
  74. -GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check)
  75. -GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx)
  76. -GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx)
  77. -GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx)
  78. -GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx)
  79. -
  80. /* Vector Single-Width Scaling Shift Instructions */
  81. GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
  82. GEN_OPIVV_TRANS(vssra_vv, opivv_check)
  83. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  84. index fb01d126d7..2bc586fbe5 100644
  85. --- a/target/riscv/vector_helper.c
  86. +++ b/target/riscv/vector_helper.c
  87. @@ -2703,211 +2703,6 @@ GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2)
  88. GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4)
  89. GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8)
  90. -/* Vector Widening Saturating Scaled Multiply-Add */
  91. -static inline uint16_t
  92. -vwsmaccu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b,
  93. - uint16_t c)
  94. -{
  95. - uint8_t round;
  96. - uint16_t res = (uint16_t)a * b;
  97. -
  98. - round = get_round(vxrm, res, 4);
  99. - res = (res >> 4) + round;
  100. - return saddu16(env, vxrm, c, res);
  101. -}
  102. -
  103. -static inline uint32_t
  104. -vwsmaccu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b,
  105. - uint32_t c)
  106. -{
  107. - uint8_t round;
  108. - uint32_t res = (uint32_t)a * b;
  109. -
  110. - round = get_round(vxrm, res, 8);
  111. - res = (res >> 8) + round;
  112. - return saddu32(env, vxrm, c, res);
  113. -}
  114. -
  115. -static inline uint64_t
  116. -vwsmaccu32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b,
  117. - uint64_t c)
  118. -{
  119. - uint8_t round;
  120. - uint64_t res = (uint64_t)a * b;
  121. -
  122. - round = get_round(vxrm, res, 16);
  123. - res = (res >> 16) + round;
  124. - return saddu64(env, vxrm, c, res);
  125. -}
  126. -
  127. -#define OPIVV3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
  128. -static inline void \
  129. -do_##NAME(void *vd, void *vs1, void *vs2, int i, \
  130. - CPURISCVState *env, int vxrm) \
  131. -{ \
  132. - TX1 s1 = *((T1 *)vs1 + HS1(i)); \
  133. - TX2 s2 = *((T2 *)vs2 + HS2(i)); \
  134. - TD d = *((TD *)vd + HD(i)); \
  135. - *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1, d); \
  136. -}
  137. -
  138. -RVVCALL(OPIVV3_RM, vwsmaccu_vv_b, WOP_UUU_B, H2, H1, H1, vwsmaccu8)
  139. -RVVCALL(OPIVV3_RM, vwsmaccu_vv_h, WOP_UUU_H, H4, H2, H2, vwsmaccu16)
  140. -RVVCALL(OPIVV3_RM, vwsmaccu_vv_w, WOP_UUU_W, H8, H4, H4, vwsmaccu32)
  141. -GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2)
  142. -GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4)
  143. -GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8)
  144. -
  145. -#define OPIVX3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
  146. -static inline void \
  147. -do_##NAME(void *vd, target_long s1, void *vs2, int i, \
  148. - CPURISCVState *env, int vxrm) \
  149. -{ \
  150. - TX2 s2 = *((T2 *)vs2 + HS2(i)); \
  151. - TD d = *((TD *)vd + HD(i)); \
  152. - *((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1, d); \
  153. -}
  154. -
  155. -RVVCALL(OPIVX3_RM, vwsmaccu_vx_b, WOP_UUU_B, H2, H1, vwsmaccu8)
  156. -RVVCALL(OPIVX3_RM, vwsmaccu_vx_h, WOP_UUU_H, H4, H2, vwsmaccu16)
  157. -RVVCALL(OPIVX3_RM, vwsmaccu_vx_w, WOP_UUU_W, H8, H4, vwsmaccu32)
  158. -GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2)
  159. -GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4)
  160. -GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8)
  161. -
  162. -static inline int16_t
  163. -vwsmacc8(CPURISCVState *env, int vxrm, int8_t a, int8_t b, int16_t c)
  164. -{
  165. - uint8_t round;
  166. - int16_t res = (int16_t)a * b;
  167. -
  168. - round = get_round(vxrm, res, 4);
  169. - res = (res >> 4) + round;
  170. - return sadd16(env, vxrm, c, res);
  171. -}
  172. -
  173. -static inline int32_t
  174. -vwsmacc16(CPURISCVState *env, int vxrm, int16_t a, int16_t b, int32_t c)
  175. -{
  176. - uint8_t round;
  177. - int32_t res = (int32_t)a * b;
  178. -
  179. - round = get_round(vxrm, res, 8);
  180. - res = (res >> 8) + round;
  181. - return sadd32(env, vxrm, c, res);
  182. -
  183. -}
  184. -
  185. -static inline int64_t
  186. -vwsmacc32(CPURISCVState *env, int vxrm, int32_t a, int32_t b, int64_t c)
  187. -{
  188. - uint8_t round;
  189. - int64_t res = (int64_t)a * b;
  190. -
  191. - round = get_round(vxrm, res, 16);
  192. - res = (res >> 16) + round;
  193. - return sadd64(env, vxrm, c, res);
  194. -}
  195. -
  196. -RVVCALL(OPIVV3_RM, vwsmacc_vv_b, WOP_SSS_B, H2, H1, H1, vwsmacc8)
  197. -RVVCALL(OPIVV3_RM, vwsmacc_vv_h, WOP_SSS_H, H4, H2, H2, vwsmacc16)
  198. -RVVCALL(OPIVV3_RM, vwsmacc_vv_w, WOP_SSS_W, H8, H4, H4, vwsmacc32)
  199. -GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2)
  200. -GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4)
  201. -GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8)
  202. -RVVCALL(OPIVX3_RM, vwsmacc_vx_b, WOP_SSS_B, H2, H1, vwsmacc8)
  203. -RVVCALL(OPIVX3_RM, vwsmacc_vx_h, WOP_SSS_H, H4, H2, vwsmacc16)
  204. -RVVCALL(OPIVX3_RM, vwsmacc_vx_w, WOP_SSS_W, H8, H4, vwsmacc32)
  205. -GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2)
  206. -GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4)
  207. -GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8)
  208. -
  209. -static inline int16_t
  210. -vwsmaccsu8(CPURISCVState *env, int vxrm, uint8_t a, int8_t b, int16_t c)
  211. -{
  212. - uint8_t round;
  213. - int16_t res = a * (int16_t)b;
  214. -
  215. - round = get_round(vxrm, res, 4);
  216. - res = (res >> 4) + round;
  217. - return ssub16(env, vxrm, c, res);
  218. -}
  219. -
  220. -static inline int32_t
  221. -vwsmaccsu16(CPURISCVState *env, int vxrm, uint16_t a, int16_t b, uint32_t c)
  222. -{
  223. - uint8_t round;
  224. - int32_t res = a * (int32_t)b;
  225. -
  226. - round = get_round(vxrm, res, 8);
  227. - res = (res >> 8) + round;
  228. - return ssub32(env, vxrm, c, res);
  229. -}
  230. -
  231. -static inline int64_t
  232. -vwsmaccsu32(CPURISCVState *env, int vxrm, uint32_t a, int32_t b, int64_t c)
  233. -{
  234. - uint8_t round;
  235. - int64_t res = a * (int64_t)b;
  236. -
  237. - round = get_round(vxrm, res, 16);
  238. - res = (res >> 16) + round;
  239. - return ssub64(env, vxrm, c, res);
  240. -}
  241. -
  242. -RVVCALL(OPIVV3_RM, vwsmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, vwsmaccsu8)
  243. -RVVCALL(OPIVV3_RM, vwsmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, vwsmaccsu16)
  244. -RVVCALL(OPIVV3_RM, vwsmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, vwsmaccsu32)
  245. -GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2)
  246. -GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4)
  247. -GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8)
  248. -RVVCALL(OPIVX3_RM, vwsmaccsu_vx_b, WOP_SSU_B, H2, H1, vwsmaccsu8)
  249. -RVVCALL(OPIVX3_RM, vwsmaccsu_vx_h, WOP_SSU_H, H4, H2, vwsmaccsu16)
  250. -RVVCALL(OPIVX3_RM, vwsmaccsu_vx_w, WOP_SSU_W, H8, H4, vwsmaccsu32)
  251. -GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2)
  252. -GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4)
  253. -GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8)
  254. -
  255. -static inline int16_t
  256. -vwsmaccus8(CPURISCVState *env, int vxrm, int8_t a, uint8_t b, int16_t c)
  257. -{
  258. - uint8_t round;
  259. - int16_t res = (int16_t)a * b;
  260. -
  261. - round = get_round(vxrm, res, 4);
  262. - res = (res >> 4) + round;
  263. - return ssub16(env, vxrm, c, res);
  264. -}
  265. -
  266. -static inline int32_t
  267. -vwsmaccus16(CPURISCVState *env, int vxrm, int16_t a, uint16_t b, int32_t c)
  268. -{
  269. - uint8_t round;
  270. - int32_t res = (int32_t)a * b;
  271. -
  272. - round = get_round(vxrm, res, 8);
  273. - res = (res >> 8) + round;
  274. - return ssub32(env, vxrm, c, res);
  275. -}
  276. -
  277. -static inline int64_t
  278. -vwsmaccus32(CPURISCVState *env, int vxrm, int32_t a, uint32_t b, int64_t c)
  279. -{
  280. - uint8_t round;
  281. - int64_t res = (int64_t)a * b;
  282. -
  283. - round = get_round(vxrm, res, 16);
  284. - res = (res >> 16) + round;
  285. - return ssub64(env, vxrm, c, res);
  286. -}
  287. -
  288. -RVVCALL(OPIVX3_RM, vwsmaccus_vx_b, WOP_SUS_B, H2, H1, vwsmaccus8)
  289. -RVVCALL(OPIVX3_RM, vwsmaccus_vx_h, WOP_SUS_H, H4, H2, vwsmaccus16)
  290. -RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4, vwsmaccus32)
  291. -GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2)
  292. -GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4)
  293. -GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8)
  294. -
  295. /* Vector Single-Width Scaling Shift Instructions */
  296. static inline uint8_t
  297. vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
  298. --
  299. 2.33.1