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- From 0c30075fced0c87205d9bec510cade4b421b14b5 Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Fri, 14 Aug 2020 17:02:24 +0800
- Subject: [PATCH 046/107] target/riscv: rvv-1.0: whole register move
- instructions
- Add the following instructions:
- * vmv1r.v
- * vmv2r.v
- * vmv4r.v
- * vmv8r.v
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- ---
- target/riscv/insn32.decode | 4 ++++
- target/riscv/insn_trans/trans_rvv.c.inc | 25 +++++++++++++++++++++++++
- 2 files changed, 29 insertions(+)
- diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
- index 41eb9628d3..230aa74c51 100644
- --- a/target/riscv/insn32.decode
- +++ b/target/riscv/insn32.decode
- @@ -625,6 +625,10 @@ vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
- vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
- vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
- vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
- +vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
- +vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
- +vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
- +vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
-
- vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
- vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
- diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
- index 39b5d9a064..d6c68587ab 100644
- --- a/target/riscv/insn_trans/trans_rvv.c.inc
- +++ b/target/riscv/insn_trans/trans_rvv.c.inc
- @@ -3494,3 +3494,28 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
- }
- return false;
- }
- +
- +/*
- + * Whole Vector Register Move Instructions ignore vtype and vl setting.
- + * Thus, we don't need to check vill bit. (Section 17.6)
- + */
- +#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
- +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
- +{ \
- + if (require_rvv(s) && \
- + QEMU_IS_ALIGNED(a->rd, LEN) && \
- + QEMU_IS_ALIGNED(a->rs2, LEN)) { \
- + /* EEW = 8 */ \
- + tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
- + vreg_ofs(s, a->rs2), \
- + s->vlen / 8 * LEN, s->vlen / 8 * LEN); \
- + mark_vs_dirty(s); \
- + return true; \
- + } \
- + return false; \
- +}
- +
- +GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
- +GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
- +GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
- +GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
- --
- 2.33.1
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