0002-Add-four-cache-csr-instruction.patch 3.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110
  1. From a32d71b0a78a30fe9a72db6b3bfaed8c5caab2e5 Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Wed, 29 Sep 2021 16:08:51 +0800
  4. Subject: [PATCH 2/2] Add four cache csr instruction
  5. ---
  6. target/riscv/helper.h | 7 +++++++
  7. target/riscv/insn32.decode | 9 +++++++++
  8. target/riscv/insn_trans/trans_rvi.c.inc | 24 ++++++++++++++++++++++++
  9. target/riscv/op_helper.c | 6 ++++++
  10. 4 files changed, 46 insertions(+)
  11. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  12. index 9f0abef25f..b14a656877 100644
  13. --- a/target/riscv/helper.h
  14. +++ b/target/riscv/helper.h
  15. @@ -136,6 +136,13 @@ DEF_HELPER_FLAGS_3(fsrw, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  16. DEF_HELPER_3(csrrw, tl, env, tl, tl)
  17. DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
  18. DEF_HELPER_4(csrrc, tl, env, tl, tl, tl)
  19. +
  20. +/* Custom Cache CSR */
  21. +DEF_HELPER_1(cflush_d_l1, void, tl)
  22. +DEF_HELPER_1(cdiscard_d_l1, void, tl)
  23. +DEF_HELPER_1(cflush_d_l2, void, tl)
  24. +DEF_HELPER_1(cdiscard_d_l2, void, tl)
  25. +
  26. #ifndef CONFIG_USER_ONLY
  27. DEF_HELPER_2(sret, tl, env, tl)
  28. DEF_HELPER_2(mret, tl, env, tl)
  29. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  30. index f4b030747c..b784946c8c 100644
  31. --- a/target/riscv/insn32.decode
  32. +++ b/target/riscv/insn32.decode
  33. @@ -96,6 +96,9 @@
  34. @sfence_vm ....... ..... ..... ... ..... ....... %rs1
  35. +# Custom Cache CSR
  36. +@csr_cache ............ ..... ... ..... ....... %rs1
  37. +
  38. # *** Privileged Instructions ***
  39. ecall 000000000000 00000 000 00000 1110011
  40. ebreak 000000000001 00000 000 00000 1110011
  41. @@ -106,6 +109,12 @@ wfi 0001000 00101 00000 000 00000 1110011
  42. sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
  43. sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
  44. +# *** Custom cache CSR ***
  45. +cflush_d_l1 111111000000 ..... 000 00000 1110011 @csr_cache
  46. +cdiscard_d_l1 111111000010 ..... 000 00000 1110011 @csr_cache
  47. +cflush_d_l2 111111000100 ..... 000 00000 1110011 @csr_cache
  48. +cdiscard_d_l2 111111000110 ..... 000 00000 1110011 @csr_cache
  49. +
  50. # *** RV32I Base Instruction Set ***
  51. lui .................... ..... 0110111 @u
  52. auipc .................... ..... 0010111 @u
  53. diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
  54. index 7b89420184..bdabeaf376 100644
  55. --- a/target/riscv/insn_trans/trans_rvi.c.inc
  56. +++ b/target/riscv/insn_trans/trans_rvi.c.inc
  57. @@ -529,3 +529,27 @@ static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
  58. RISCV_OP_CSR_POST;
  59. return true;
  60. }
  61. +
  62. +static bool trans_cflush_d_l1(DisasContext *ctx, arg_cflush_d_l1 *a)
  63. +{
  64. + gen_helper_cflush_d_l1(cpu_gpr[a->rs1]);
  65. + return true;
  66. +}
  67. +
  68. +static bool trans_cdiscard_d_l1(DisasContext *ctx, arg_cflush_d_l1 *a)
  69. +{
  70. + gen_helper_cdiscard_d_l1(cpu_gpr[a->rs1]);
  71. + return true;
  72. +}
  73. +
  74. +static bool trans_cflush_d_l2(DisasContext *ctx, arg_cflush_d_l1 *a)
  75. +{
  76. + gen_helper_cflush_d_l2(cpu_gpr[a->rs1]);
  77. + return true;
  78. +}
  79. +
  80. +static bool trans_cdiscard_d_l2(DisasContext *ctx, arg_cflush_d_l1 *a)
  81. +{
  82. + gen_helper_cdiscard_d_l2(cpu_gpr[a->rs1]);
  83. + return true;
  84. +}
  85. \ No newline at end of file
  86. diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
  87. index 1eddcb94de..8d034236ee 100644
  88. --- a/target/riscv/op_helper.c
  89. +++ b/target/riscv/op_helper.c
  90. @@ -74,6 +74,12 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
  91. return val;
  92. }
  93. +void helper_cflush_d_l1(target_ulong rs1) {}
  94. +void helper_cdiscard_d_l1(target_ulong rs1) {}
  95. +void helper_cflush_d_l2(target_ulong rs1) {}
  96. +void helper_cdiscard_d_l2(target_ulong rs1) {}
  97. +
  98. +
  99. #ifndef CONFIG_USER_ONLY
  100. target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
  101. --
  102. 2.33.1