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- From ba89af6905dd35a3813fd8a12c327c12fb2efddc Mon Sep 17 00:00:00 2001
- From: Nelson Chu <nelson.chu@sifive.com>
- Date: Thu, 13 Aug 2020 17:27:33 +0800
- Subject: [PATCH 26/48] RISC-V: Fix the constraints for vector mask and
- compress instructions.
- Add the missing constraints for vmsbf.m, vmsif.m and vmsof.m. Their
- destination vector register can not overlap the source register.
- Besides, we don't need to check the VM overlap for vcompress.vm, so
- change the match_func from match_vd_neq_vs1_neq_vs2 to
- match_vd_neq_vs1_neq_vs2_neq_vm.
- opcodes/
- * riscv-opc.c (match_vd_neq_vs1_neq_vs2): New function. Only
- check if VD is overlap VS2.
- (riscv_opcodes): We don't need to check the VM overlap for
- vcompress.vm, so change the match_func to match_vd_neq_vs1_neq_vs2.
- gas/
- * testsuite/gas/riscv/vector-insns-fail-mask.l: Add the missing
- overlap failed cases for vmsbf.m, vmsif.m and vmsof.m.
- * testsuite/gas/riscv/vector-insns-fail-mask.s: Likewise.
- ---
- .../gas/riscv/vector-insns-fail-mask.l | 3 +++
- .../gas/riscv/vector-insns-fail-mask.s | 3 +++
- opcodes/riscv-opc.c | 25 ++++++++++++++++---
- 3 files changed, 27 insertions(+), 4 deletions(-)
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.l b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
- index 5c4e881489..3b23becc16 100644
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
- @@ -1,6 +1,9 @@
- .*: Assembler messages:
- +.*Error: illegal operands `vmsbf.m v4,v4'
- .*Error: illegal operands `vmsbf.m v0,v4,v0.t'
- +.*Error: illegal operands `vmsif.m v4,v4'
- .*Error: illegal operands `vmsif.m v0,v4,v0.t'
- +.*Error: illegal operands `vmsof.m v4,v4'
- .*Error: illegal operands `vmsof.m v0,v4,v0.t'
- .*Error: illegal operands `viota.m v4,v4'
- .*Error: illegal operands `viota.m v0,v4,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.s b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
- index 580b101c77..99b19f6bdd 100644
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
- @@ -1,13 +1,16 @@
- # Vector Set-before-first Mask Bit
-
- + vmsbf.m v4, v4 # vd overlap vs2
- vmsbf.m v0, v4, v0.t # vd overlap vm
-
- # Vector Set-including-first Mask Bit
-
- + vmsif.m v4, v4 # vd overlap vs2
- vmsif.m v0, v4, v0.t # vd overlap vm
-
- # Vector Set-only-first Mask Bit
-
- + vmsof.m v4, v4 # vd overlap vs2
- vmsof.m v0, v4, v0.t # vd overlap vm
-
- # Vector Iota Instruction
- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
- index 843b94aa46..2d78218e2b 100644
- --- a/opcodes/riscv-opc.c
- +++ b/opcodes/riscv-opc.c
- @@ -398,6 +398,23 @@ match_narrow_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
- return match_opcode (op, insn, 0);
- }
-
- +static int
- +match_vd_neq_vs1_neq_vs2 (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- +{
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- +
- + if (constraints
- + && (vs1 == vd
- + || vs2 == vd))
- + return 0;
- +
- + return match_opcode (op, insn, 0);
- +}
- +
- static int
- match_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
- insn_t insn,
- @@ -2013,9 +2030,9 @@ const struct riscv_opcode riscv_opcodes[] =
-
- {"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
- {"vfirst.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
- -{"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vm, 0},
- -{"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vm, 0},
- -{"vmsof.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vm, 0},
- +{"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0},
- +{"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0},
- +{"vmsof.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vs2_neq_vm, 0},
- {"viota.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
- {"vid.v", 0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
-
- @@ -2040,7 +2057,7 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vrgather.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
- {"vrgatherei16.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHEREI16VV, MASK_VRGATHEREI16VV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
-
- -{"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2, 0},
-
- {"vmv1r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
- {"vmv2r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_vmv_nf_rv, 0},
- --
- 2.33.0
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