0026-RISC-V-Fix-the-constraints-for-vector-mask-and-compr.patch 4.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117
  1. From ba89af6905dd35a3813fd8a12c327c12fb2efddc Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Thu, 13 Aug 2020 17:27:33 +0800
  4. Subject: [PATCH 26/48] RISC-V: Fix the constraints for vector mask and
  5. compress instructions.
  6. Add the missing constraints for vmsbf.m, vmsif.m and vmsof.m. Their
  7. destination vector register can not overlap the source register.
  8. Besides, we don't need to check the VM overlap for vcompress.vm, so
  9. change the match_func from match_vd_neq_vs1_neq_vs2 to
  10. match_vd_neq_vs1_neq_vs2_neq_vm.
  11. opcodes/
  12. * riscv-opc.c (match_vd_neq_vs1_neq_vs2): New function. Only
  13. check if VD is overlap VS2.
  14. (riscv_opcodes): We don't need to check the VM overlap for
  15. vcompress.vm, so change the match_func to match_vd_neq_vs1_neq_vs2.
  16. gas/
  17. * testsuite/gas/riscv/vector-insns-fail-mask.l: Add the missing
  18. overlap failed cases for vmsbf.m, vmsif.m and vmsof.m.
  19. * testsuite/gas/riscv/vector-insns-fail-mask.s: Likewise.
  20. ---
  21. .../gas/riscv/vector-insns-fail-mask.l | 3 +++
  22. .../gas/riscv/vector-insns-fail-mask.s | 3 +++
  23. opcodes/riscv-opc.c | 25 ++++++++++++++++---
  24. 3 files changed, 27 insertions(+), 4 deletions(-)
  25. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.l b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
  26. index 5c4e881489..3b23becc16 100644
  27. --- a/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
  28. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
  29. @@ -1,6 +1,9 @@
  30. .*: Assembler messages:
  31. +.*Error: illegal operands `vmsbf.m v4,v4'
  32. .*Error: illegal operands `vmsbf.m v0,v4,v0.t'
  33. +.*Error: illegal operands `vmsif.m v4,v4'
  34. .*Error: illegal operands `vmsif.m v0,v4,v0.t'
  35. +.*Error: illegal operands `vmsof.m v4,v4'
  36. .*Error: illegal operands `vmsof.m v0,v4,v0.t'
  37. .*Error: illegal operands `viota.m v4,v4'
  38. .*Error: illegal operands `viota.m v0,v4,v0.t'
  39. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.s b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
  40. index 580b101c77..99b19f6bdd 100644
  41. --- a/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
  42. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
  43. @@ -1,13 +1,16 @@
  44. # Vector Set-before-first Mask Bit
  45. + vmsbf.m v4, v4 # vd overlap vs2
  46. vmsbf.m v0, v4, v0.t # vd overlap vm
  47. # Vector Set-including-first Mask Bit
  48. + vmsif.m v4, v4 # vd overlap vs2
  49. vmsif.m v0, v4, v0.t # vd overlap vm
  50. # Vector Set-only-first Mask Bit
  51. + vmsof.m v4, v4 # vd overlap vs2
  52. vmsof.m v0, v4, v0.t # vd overlap vm
  53. # Vector Iota Instruction
  54. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  55. index 843b94aa46..2d78218e2b 100644
  56. --- a/opcodes/riscv-opc.c
  57. +++ b/opcodes/riscv-opc.c
  58. @@ -398,6 +398,23 @@ match_narrow_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
  59. return match_opcode (op, insn, 0);
  60. }
  61. +static int
  62. +match_vd_neq_vs1_neq_vs2 (const struct riscv_opcode *op,
  63. + insn_t insn,
  64. + int constraints)
  65. +{
  66. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  67. + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
  68. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  69. +
  70. + if (constraints
  71. + && (vs1 == vd
  72. + || vs2 == vd))
  73. + return 0;
  74. +
  75. + return match_opcode (op, insn, 0);
  76. +}
  77. +
  78. static int
  79. match_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
  80. insn_t insn,
  81. @@ -2013,9 +2030,9 @@ const struct riscv_opcode riscv_opcodes[] =
  82. {"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
  83. {"vfirst.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
  84. -{"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vm, 0},
  85. -{"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vm, 0},
  86. -{"vmsof.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vm, 0},
  87. +{"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0},
  88. +{"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0},
  89. +{"vmsof.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vs2_neq_vm, 0},
  90. {"viota.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
  91. {"vid.v", 0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
  92. @@ -2040,7 +2057,7 @@ const struct riscv_opcode riscv_opcodes[] =
  93. {"vrgather.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
  94. {"vrgatherei16.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHEREI16VV, MASK_VRGATHEREI16VV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
  95. -{"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
  96. +{"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2, 0},
  97. {"vmv1r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
  98. {"vmv2r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_vmv_nf_rv, 0},
  99. --
  100. 2.33.0