0025-RISC-V-Add-the-missing-constraints-for-VL-nf-R-and-V.patch 14 KB

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  1. From 03a170a6d30138901805e77e48c00085573a409a Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Thu, 13 Aug 2020 17:03:26 +0800
  4. Subject: [PATCH 25/48] RISC-V: Add the missing constraints for VL<nf>R and
  5. VS<nf>R.
  6. The destination vector register must be aligned to <nf>. The <nf>
  7. is 1, 2, 4, 8 for now. Besides, under the aligned constraints, it
  8. is impossible to use the registers that don't exist (number > 31).
  9. opcodes/
  10. * riscv-opc.c (match_vls_nf_rv): New function. It is used to
  11. check the constraints for VL<nf>R and VS<nf>R.
  12. (riscv_opcodes): Updated the match_func for VL<nf>R and VS<nf>R.
  13. gas/
  14. * testsuite/gas/riscv/vector-insns-fail-load-store.l: Add the
  15. unaligned failed cases for VL<nf>R and VS<nf>R.
  16. * testsuite/gas/riscv/vector-insns-fail-load-store.s: Likewise.
  17. ---
  18. .../gas/riscv/vector-insns-fail-load-store.l | 30 +++++
  19. .../gas/riscv/vector-insns-fail-load-store.s | 38 +++++++
  20. opcodes/riscv-opc.c | 103 ++++++++++--------
  21. 3 files changed, 127 insertions(+), 44 deletions(-)
  22. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
  23. index bd04cbb263..406d79e2b2 100644
  24. --- a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
  25. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
  26. @@ -555,3 +555,33 @@
  27. .*Error: illegal operands `vlxseg8ei1024.v v0,\(a0\),v4,v0.t'
  28. .*Error: illegal operands `vsxseg8ei1024.v v4,\(a0\),v4'
  29. .*Error: illegal operands `vsxseg8ei1024.v v0,\(a0\),v4,v0.t'
  30. +.*Error: illegal operands `vl2r.v v31,\(a0\)'
  31. +.*Error: illegal operands `vl2re8.v v31,\(a0\)'
  32. +.*Error: illegal operands `vl2re16.v v31,\(a0\)'
  33. +.*Error: illegal operands `vl2re32.v v31,\(a0\)'
  34. +.*Error: illegal operands `vl2re64.v v31,\(a0\)'
  35. +.*Error: illegal operands `vl2re128.v v31,\(a0\)'
  36. +.*Error: illegal operands `vl2re256.v v31,\(a0\)'
  37. +.*Error: illegal operands `vl2re512.v v31,\(a0\)'
  38. +.*Error: illegal operands `vl2re1024.v v31,\(a0\)'
  39. +.*Error: illegal operands `vl4r.v v30,\(a0\)'
  40. +.*Error: illegal operands `vl4re8.v v30,\(a0\)'
  41. +.*Error: illegal operands `vl4re16.v v30,\(a0\)'
  42. +.*Error: illegal operands `vl4re32.v v30,\(a0\)'
  43. +.*Error: illegal operands `vl4re64.v v30,\(a0\)'
  44. +.*Error: illegal operands `vl4re128.v v30,\(a0\)'
  45. +.*Error: illegal operands `vl4re256.v v30,\(a0\)'
  46. +.*Error: illegal operands `vl4re512.v v30,\(a0\)'
  47. +.*Error: illegal operands `vl4re1024.v v30,\(a0\)'
  48. +.*Error: illegal operands `vl8r.v v26,\(a0\)'
  49. +.*Error: illegal operands `vl8re8.v v26,\(a0\)'
  50. +.*Error: illegal operands `vl8re16.v v26,\(a0\)'
  51. +.*Error: illegal operands `vl8re32.v v26,\(a0\)'
  52. +.*Error: illegal operands `vl8re64.v v26,\(a0\)'
  53. +.*Error: illegal operands `vl8re128.v v26,\(a0\)'
  54. +.*Error: illegal operands `vl8re256.v v26,\(a0\)'
  55. +.*Error: illegal operands `vl8re512.v v26,\(a0\)'
  56. +.*Error: illegal operands `vl8re1024.v v26,\(a0\)'
  57. +.*Error: illegal operands `vs2r.v v31,\(a0\)'
  58. +.*Error: illegal operands `vs4r.v v30,\(a0\)'
  59. +.*Error: illegal operands `vs8r.v v26,\(a0\)'
  60. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
  61. index 05f9358aed..e4f1085174 100644
  62. --- a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
  63. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
  64. @@ -608,3 +608,41 @@
  65. vlxseg8ei1024.v v0, (a0), v4, v0.t
  66. vsxseg8ei1024.v v4, (a0), v4
  67. vsxseg8ei1024.v v0, (a0), v4, v0.t
  68. +
  69. +# Vector Load/Store Whole Register Instructions
  70. +
  71. + vl1r.v v31, (a0) # OK
  72. +
  73. + vl2r.v v31, (a0) # vd must be aligned to 2
  74. + vl2re8.v v31, (a0)
  75. + vl2re16.v v31, (a0)
  76. + vl2re32.v v31, (a0)
  77. + vl2re64.v v31, (a0)
  78. + vl2re128.v v31, (a0)
  79. + vl2re256.v v31, (a0)
  80. + vl2re512.v v31, (a0)
  81. + vl2re1024.v v31, (a0)
  82. +
  83. + vl4r.v v30, (a0) # vd must be aligned to 4
  84. + vl4re8.v v30, (a0)
  85. + vl4re16.v v30, (a0)
  86. + vl4re32.v v30, (a0)
  87. + vl4re64.v v30, (a0)
  88. + vl4re128.v v30, (a0)
  89. + vl4re256.v v30, (a0)
  90. + vl4re512.v v30, (a0)
  91. + vl4re1024.v v30, (a0)
  92. +
  93. + vl8r.v v26, (a0) # vd must be aligned to 8
  94. + vl8re8.v v26, (a0)
  95. + vl8re16.v v26, (a0)
  96. + vl8re32.v v26, (a0)
  97. + vl8re64.v v26, (a0)
  98. + vl8re128.v v26, (a0)
  99. + vl8re256.v v26, (a0)
  100. + vl8re512.v v26, (a0)
  101. + vl8re1024.v v26, (a0)
  102. +
  103. + vs2r.v v31, (a0) # vs3 must be aligned to 2
  104. + vs4r.v v30, (a0) # vs3 must be aligned to 4
  105. + vs8r.v v26, (a0) # vs3 must be aligned to 8
  106. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  107. index 58190fd7c9..843b94aa46 100644
  108. --- a/opcodes/riscv-opc.c
  109. +++ b/opcodes/riscv-opc.c
  110. @@ -453,6 +453,21 @@ match_vd_neq_vm (const struct riscv_opcode *op,
  111. return match_opcode (op, insn, 0);
  112. }
  113. +static int
  114. +match_vls_nf_rv (const struct riscv_opcode *op,
  115. + insn_t insn,
  116. + int constraints)
  117. +{
  118. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  119. + int nf = ((insn & (0x7 << 29) ) >> 29) + 1;
  120. +
  121. + if (constraints
  122. + && ((vd % nf) != 0))
  123. + return 0;
  124. +
  125. + return match_opcode (op, insn, 0);
  126. +}
  127. +
  128. static int
  129. match_vmv_nf_rv (const struct riscv_opcode *op,
  130. insn_t insn,
  131. @@ -1543,50 +1558,50 @@ const struct riscv_opcode riscv_opcodes[] =
  132. {"vlseg7e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E1024FFV, MASK_VLSEG7E1024FFV, match_vd_neq_vm, INSN_DREF },
  133. {"vlseg8e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E1024FFV, MASK_VLSEG8E1024FFV, match_vd_neq_vm, INSN_DREF },
  134. -{"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
  135. -{"vl1re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF },
  136. -{"vl1re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_opcode, INSN_DREF },
  137. -{"vl1re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_opcode, INSN_DREF },
  138. -{"vl1re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_opcode, INSN_DREF },
  139. -{"vl1re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE128V, MASK_VL1RE128V, match_opcode, INSN_DREF },
  140. -{"vl1re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE256V, MASK_VL1RE256V, match_opcode, INSN_DREF },
  141. -{"vl1re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE512V, MASK_VL1RE512V, match_opcode, INSN_DREF },
  142. -{"vl1re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE1024V, MASK_VL1RE1024V, match_opcode, INSN_DREF },
  143. -
  144. -{"vl2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
  145. -{"vl2re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF },
  146. -{"vl2re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_opcode, INSN_DREF },
  147. -{"vl2re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_opcode, INSN_DREF },
  148. -{"vl2re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_opcode, INSN_DREF },
  149. -{"vl2re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE128V, MASK_VL2RE128V, match_opcode, INSN_DREF },
  150. -{"vl2re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE256V, MASK_VL2RE256V, match_opcode, INSN_DREF },
  151. -{"vl2re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE512V, MASK_VL2RE512V, match_opcode, INSN_DREF },
  152. -{"vl2re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE1024V, MASK_VL2RE1024V, match_opcode, INSN_DREF },
  153. -
  154. -{"vl4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
  155. -{"vl4re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF },
  156. -{"vl4re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_opcode, INSN_DREF },
  157. -{"vl4re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_opcode, INSN_DREF },
  158. -{"vl4re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_opcode, INSN_DREF },
  159. -{"vl4re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE128V, MASK_VL4RE128V, match_opcode, INSN_DREF },
  160. -{"vl4re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE256V, MASK_VL4RE256V, match_opcode, INSN_DREF },
  161. -{"vl4re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE512V, MASK_VL4RE512V, match_opcode, INSN_DREF },
  162. -{"vl4re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE1024V, MASK_VL4RE1024V, match_opcode, INSN_DREF },
  163. -
  164. -{"vl8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF|INSN_ALIAS },
  165. -{"vl8re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF },
  166. -{"vl8re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_opcode, INSN_DREF },
  167. -{"vl8re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_opcode, INSN_DREF },
  168. -{"vl8re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_opcode, INSN_DREF },
  169. -{"vl8re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE128V, MASK_VL8RE128V, match_opcode, INSN_DREF },
  170. -{"vl8re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE256V, MASK_VL8RE256V, match_opcode, INSN_DREF },
  171. -{"vl8re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE512V, MASK_VL8RE512V, match_opcode, INSN_DREF },
  172. -{"vl8re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE1024V, MASK_VL8RE1024V, match_opcode, INSN_DREF },
  173. -
  174. -{"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_opcode, INSN_DREF },
  175. -{"vs2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_opcode, INSN_DREF },
  176. -{"vs4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_opcode, INSN_DREF },
  177. -{"vs8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_opcode, INSN_DREF },
  178. +{"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
  179. +{"vl1re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF },
  180. +{"vl1re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_vls_nf_rv, INSN_DREF },
  181. +{"vl1re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_vls_nf_rv, INSN_DREF },
  182. +{"vl1re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_vls_nf_rv, INSN_DREF },
  183. +{"vl1re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE128V, MASK_VL1RE128V, match_vls_nf_rv, INSN_DREF },
  184. +{"vl1re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE256V, MASK_VL1RE256V, match_vls_nf_rv, INSN_DREF },
  185. +{"vl1re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE512V, MASK_VL1RE512V, match_vls_nf_rv, INSN_DREF },
  186. +{"vl1re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE1024V, MASK_VL1RE1024V, match_vls_nf_rv, INSN_DREF },
  187. +
  188. +{"vl2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
  189. +{"vl2re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF },
  190. +{"vl2re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_vls_nf_rv, INSN_DREF },
  191. +{"vl2re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_vls_nf_rv, INSN_DREF },
  192. +{"vl2re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_vls_nf_rv, INSN_DREF },
  193. +{"vl2re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE128V, MASK_VL2RE128V, match_vls_nf_rv, INSN_DREF },
  194. +{"vl2re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE256V, MASK_VL2RE256V, match_vls_nf_rv, INSN_DREF },
  195. +{"vl2re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE512V, MASK_VL2RE512V, match_vls_nf_rv, INSN_DREF },
  196. +{"vl2re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE1024V, MASK_VL2RE1024V, match_vls_nf_rv, INSN_DREF },
  197. +
  198. +{"vl4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
  199. +{"vl4re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF },
  200. +{"vl4re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_vls_nf_rv, INSN_DREF },
  201. +{"vl4re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_vls_nf_rv, INSN_DREF },
  202. +{"vl4re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_vls_nf_rv, INSN_DREF },
  203. +{"vl4re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE128V, MASK_VL4RE128V, match_vls_nf_rv, INSN_DREF },
  204. +{"vl4re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE256V, MASK_VL4RE256V, match_vls_nf_rv, INSN_DREF },
  205. +{"vl4re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE512V, MASK_VL4RE512V, match_vls_nf_rv, INSN_DREF },
  206. +{"vl4re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE1024V, MASK_VL4RE1024V, match_vls_nf_rv, INSN_DREF },
  207. +
  208. +{"vl8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
  209. +{"vl8re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF },
  210. +{"vl8re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_vls_nf_rv, INSN_DREF },
  211. +{"vl8re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_vls_nf_rv, INSN_DREF },
  212. +{"vl8re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_vls_nf_rv, INSN_DREF },
  213. +{"vl8re128.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE128V, MASK_VL8RE128V, match_vls_nf_rv, INSN_DREF },
  214. +{"vl8re256.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE256V, MASK_VL8RE256V, match_vls_nf_rv, INSN_DREF },
  215. +{"vl8re512.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE512V, MASK_VL8RE512V, match_vls_nf_rv, INSN_DREF },
  216. +{"vl8re1024.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE1024V, MASK_VL8RE1024V, match_vls_nf_rv, INSN_DREF },
  217. +
  218. +{"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_vls_nf_rv, INSN_DREF },
  219. +{"vs2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_vls_nf_rv, INSN_DREF },
  220. +{"vs4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_vls_nf_rv, INSN_DREF },
  221. +{"vs8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_vls_nf_rv, INSN_DREF },
  222. {"vamoaddei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
  223. {"vamoswapei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
  224. --
  225. 2.33.0