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- From 7f2e74524afaeef6ad75cc0205406ef479173bd8 Mon Sep 17 00:00:00 2001
- From: Hsiangkai Wang <kai.wang@sifive.com>
- Date: Fri, 21 Aug 2020 16:10:16 +0800
- Subject: [PATCH 23/48] RISC-V: Convert CSR dwarf numbers to gdb register
- numbers.
- ---
- gdb/riscv-tdep.c | 3 +++
- gdb/riscv-tdep.h | 2 ++
- 2 files changed, 5 insertions(+)
- diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
- index b86ba63054..7f0c14d0ba 100644
- --- a/gdb/riscv-tdep.c
- +++ b/gdb/riscv-tdep.c
- @@ -3150,6 +3150,9 @@ riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
- else if (reg < RISCV_DWARF_REGNUM_F31)
- return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0);
-
- + else if (RISCV_DWARF_REGNUM_CSR_BEGIN <= reg && reg <= RISCV_DWARF_REGNUM_CSR_END)
- + return RISCV_FIRST_CSR_REGNUM + (reg - RISCV_DWARF_REGNUM_CSR_BEGIN);
- +
- return -1;
- }
-
- diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
- index 0ff555b063..fc5adedad3 100644
- --- a/gdb/riscv-tdep.h
- +++ b/gdb/riscv-tdep.h
- @@ -63,6 +63,8 @@ enum
- RISCV_DWARF_REGNUM_X31 = 31,
- RISCV_DWARF_REGNUM_F0 = 32,
- RISCV_DWARF_REGNUM_F31 = 63,
- + RISCV_DWARF_REGNUM_CSR_BEGIN = 4096,
- + RISCV_DWARF_REGNUM_CSR_END = 8191,
- };
-
- /* RISC-V specific per-architecture information. */
- --
- 2.33.0
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