0015-Add-assembly-pseudo-instructions-vncvt.x.x.v.patch 4.4 KB

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  1. From ed4bec347a9a77c8845a43d6dfe23317bc8091e0 Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Mon, 6 Jul 2020 14:31:14 +0800
  4. Subject: [PATCH 15/48] Add assembly pseudo instructions vncvt.x.x.v.
  5. An integer value can be halved in width using the narrowing integer
  6. shift instructions with a scalar operand of x0. Can define assembly
  7. pseudo instruction "vncvt.x.x.v vd,vs,vm" to "vnsrl.wx vd,vs,x0,vm".
  8. ---
  9. gas/testsuite/gas/riscv/vector-insns-fail-05.l | 3 +++
  10. gas/testsuite/gas/riscv/vector-insns-fail-05.s | 6 ++++++
  11. gas/testsuite/gas/riscv/vector-insns.d | 2 ++
  12. gas/testsuite/gas/riscv/vector-insns.s | 4 ++++
  13. include/opcode/riscv-opc.h | 3 +++
  14. opcodes/riscv-opc.c | 2 ++
  15. 6 files changed, 20 insertions(+)
  16. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.l b/gas/testsuite/gas/riscv/vector-insns-fail-05.l
  17. index fa519ffcf9..f2bee3d1e0 100644
  18. --- a/gas/testsuite/gas/riscv/vector-insns-fail-05.l
  19. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-05.l
  20. @@ -1,4 +1,7 @@
  21. .*: Assembler messages:
  22. +.*Error: illegal operands `vncvt.x.x.v v2,v2'
  23. +.*Error: illegal operands `vncvt.x.x.v v2,v3'
  24. +.*Error: illegal operands `vncvt.x.x.v v3,v2'
  25. .*Error: illegal operands `vnsrl.wv v2,v2,v4'
  26. .*Error: illegal operands `vnsrl.wv v2,v3,v4'
  27. .*Error: illegal operands `vnsrl.wv v3,v2,v4'
  28. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.s b/gas/testsuite/gas/riscv/vector-insns-fail-05.s
  29. index 2ec027299c..6b68680fd9 100644
  30. --- a/gas/testsuite/gas/riscv/vector-insns-fail-05.s
  31. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-05.s
  32. @@ -1,5 +1,11 @@
  33. # Narrowing Vector Arithmetic Instructions
  34. + vncvt.x.x.v v0, v2 # OK
  35. + vncvt.x.x.v v2, v2 # vd overlap vs2
  36. + vncvt.x.x.v v2, v3 # vs2 should be multiple of 2
  37. + vncvt.x.x.v v3, v2 # vd overlap vs2
  38. + vncvt.x.x.v v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  39. +
  40. vnsrl.wv v0, v2, v4 # OK
  41. vnsrl.wv v2, v2, v4 # vd overlap vs2
  42. vnsrl.wv v2, v3, v4 # vs2 should be multiple of 2
  43. diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
  44. index 634ff2945c..99eb5abf70 100644
  45. --- a/gas/testsuite/gas/riscv/vector-insns.d
  46. +++ b/gas/testsuite/gas/riscv/vector-insns.d
  47. @@ -1796,6 +1796,8 @@ Disassembly of section .text:
  48. [ ]+[0-9a-f]+:[ ]+a485c257[ ]+vsra.vx[ ]+v4,v8,a1,v0.t
  49. [ ]+[0-9a-f]+:[ ]+a480b257[ ]+vsra.vi[ ]+v4,v8,1,v0.t
  50. [ ]+[0-9a-f]+:[ ]+a48fb257[ ]+vsra.vi[ ]+v4,v8,31,v0.t
  51. +[ ]+[0-9a-f]+:[ ]+b2804257[ ]+vncvt.x.x.v[ ]+v4,v8
  52. +[ ]+[0-9a-f]+:[ ]+b0804257[ ]+vncvt.x.x.v[ ]+v4,v8,v0.t
  53. [ ]+[0-9a-f]+:[ ]+b2860257[ ]+vnsrl.wv[ ]+v4,v8,v12
  54. [ ]+[0-9a-f]+:[ ]+b285c257[ ]+vnsrl.wx[ ]+v4,v8,a1
  55. [ ]+[0-9a-f]+:[ ]+b280b257[ ]+vnsrl.wi[ ]+v4,v8,1
  56. diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
  57. index e6cfcad9ba..3b489685c9 100644
  58. --- a/gas/testsuite/gas/riscv/vector-insns.s
  59. +++ b/gas/testsuite/gas/riscv/vector-insns.s
  60. @@ -2076,6 +2076,10 @@
  61. vsra.vi v4, v8, 1, v0.t
  62. vsra.vi v4, v8, 31, v0.t
  63. + # Aliases
  64. + vncvt.x.x.v v4, v8
  65. + vncvt.x.x.v v4, v8, v0.t
  66. +
  67. vnsrl.wv v4, v8, v12
  68. vnsrl.wx v4, v8, a1
  69. vnsrl.wi v4, v8, 1
  70. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  71. index e196e27736..4e4ecc91d0 100644
  72. --- a/include/opcode/riscv-opc.h
  73. +++ b/include/opcode/riscv-opc.h
  74. @@ -2096,6 +2096,9 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
  75. #define MATCH_VSRAVI 0xa4003057
  76. #define MASK_VSRAVI 0xfc00707f
  77. +#define MATCH_VNCVTXXV 0xb0004057
  78. +#define MASK_VNCVTXXV 0xfc0ff07f
  79. +
  80. #define MATCH_VNSRLWV 0xb0000057
  81. #define MASK_VNSRLWV 0xfc00707f
  82. #define MATCH_VNSRLWX 0xb0004057
  83. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  84. index 475c65d7e5..66c3046150 100644
  85. --- a/opcodes/riscv-opc.c
  86. +++ b/opcodes/riscv-opc.c
  87. @@ -1673,6 +1673,8 @@ const struct riscv_opcode riscv_opcodes[] =
  88. {"vsra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 },
  89. {"vsra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 },
  90. +{"vncvt.x.x.v",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXV, MASK_VNCVTXXV, match_narrow_vd_neq_vs2, INSN_ALIAS },
  91. +
  92. {"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2, 0 },
  93. {"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2, 0 },
  94. {"vnsrl.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2, 0 },
  95. --
  96. 2.33.0