0002-Make-the-riscv-sim-testsuite-work.patch 1.0 KB

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  1. From f9922f1710db5d7a4e456c1a910c79b48d284c7c Mon Sep 17 00:00:00 2001
  2. From: Jim Wilson <jimw@sifive.com>
  3. Date: Tue, 17 Nov 2020 16:51:22 -0800
  4. Subject: [PATCH 02/48] Make the riscv sim testsuite work.
  5. ---
  6. sim/testsuite/sim/riscv/allinsn.exp | 2 +-
  7. sim/testsuite/sim/riscv/testutils.inc | 1 +
  8. 2 files changed, 2 insertions(+), 1 deletion(-)
  9. diff --git a/sim/testsuite/sim/riscv/allinsn.exp b/sim/testsuite/sim/riscv/allinsn.exp
  10. index 4ed7cff5d2..8553a795a5 100644
  11. --- a/sim/testsuite/sim/riscv/allinsn.exp
  12. +++ b/sim/testsuite/sim/riscv/allinsn.exp
  13. @@ -1,6 +1,6 @@
  14. # mcore simulator testsuite
  15. -if [istarget riscv-*] {
  16. +if [istarget riscv*-*] {
  17. # all machines
  18. set all_machs "riscv"
  19. diff --git a/sim/testsuite/sim/riscv/testutils.inc b/sim/testsuite/sim/riscv/testutils.inc
  20. index bb92ac0f4d..b5467ebeab 100644
  21. --- a/sim/testsuite/sim/riscv/testutils.inc
  22. +++ b/sim/testsuite/sim/riscv/testutils.inc
  23. @@ -3,6 +3,7 @@
  24. li a0, \nr
  25. # The exit utility function.
  26. li a7, 93;
  27. + ecall
  28. .endm
  29. # MACRO: pass
  30. --
  31. 2.33.0