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- From f9922f1710db5d7a4e456c1a910c79b48d284c7c Mon Sep 17 00:00:00 2001
- From: Jim Wilson <jimw@sifive.com>
- Date: Tue, 17 Nov 2020 16:51:22 -0800
- Subject: [PATCH 02/48] Make the riscv sim testsuite work.
- ---
- sim/testsuite/sim/riscv/allinsn.exp | 2 +-
- sim/testsuite/sim/riscv/testutils.inc | 1 +
- 2 files changed, 2 insertions(+), 1 deletion(-)
- diff --git a/sim/testsuite/sim/riscv/allinsn.exp b/sim/testsuite/sim/riscv/allinsn.exp
- index 4ed7cff5d2..8553a795a5 100644
- --- a/sim/testsuite/sim/riscv/allinsn.exp
- +++ b/sim/testsuite/sim/riscv/allinsn.exp
- @@ -1,6 +1,6 @@
- # mcore simulator testsuite
-
- -if [istarget riscv-*] {
- +if [istarget riscv*-*] {
- # all machines
- set all_machs "riscv"
-
- diff --git a/sim/testsuite/sim/riscv/testutils.inc b/sim/testsuite/sim/riscv/testutils.inc
- index bb92ac0f4d..b5467ebeab 100644
- --- a/sim/testsuite/sim/riscv/testutils.inc
- +++ b/sim/testsuite/sim/riscv/testutils.inc
- @@ -3,6 +3,7 @@
- li a0, \nr
- # The exit utility function.
- li a7, 93;
- + ecall
- .endm
-
- # MACRO: pass
- --
- 2.33.0
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