0007-add-customer-pref-insn-support.patch 6.0 KB

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  1. From 6841e87e31c51c92f5aeb86ac8033ed53bd67a45 Mon Sep 17 00:00:00 2001
  2. From: "max.ma" <max.ma@starfivetech.com>
  3. Date: Tue, 6 Dec 2022 23:05:47 -0800
  4. Subject: [PATCH 7/7] add customer pref insn support
  5. ---
  6. gas/config/tc-riscv.c | 42 ++++++++++++++++++++++++++++++++++++++
  7. include/opcode/riscv-opc.h | 1 +
  8. include/opcode/riscv.h | 9 ++++++++
  9. opcodes/riscv-dis.c | 7 +++++++
  10. opcodes/riscv-opc.c | 1 +
  11. 5 files changed, 60 insertions(+)
  12. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  13. index bb5f6e4aed..5112322c4a 100644
  14. --- a/gas/config/tc-riscv.c
  15. +++ b/gas/config/tc-riscv.c
  16. @@ -1154,6 +1154,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
  17. case ')': break;
  18. case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
  19. case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
  20. + case '#': used_bits |= ENCODE_PREF_TIMM (-1U); break;
  21. + case '+': used_bits |= ENCODE_PREF_SIMM (-1U); break;
  22. case 'A': break; /* Macro operand, must be symbol. */
  23. case 'B': break; /* Macro operand, must be symbol or constant. */
  24. case 'I': break; /* Macro operand, must be constant. */
  25. @@ -1553,6 +1555,27 @@ check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
  26. normalize_constant_expr (ex);
  27. }
  28. +/* The pref type should be one of the following:
  29. + 0000 - scalar prefetch L1, fetch data as if for a normal scalar load,
  30. + and imply load into all lower cache destination levels.
  31. + 0001 - scalar prefetch L2, fetch data and place the cache-line into L2,
  32. + and imply load into all lower cache destination levels.
  33. + 0010 - scalar prefetch L3, fetch data and place the cache-line into L3,
  34. + and imply load into all lower cache destination levels.
  35. + 0011 - scalar prefetch L4, fetch data and place the cache-line into L4,
  36. + and imply load into all lower cache destination levels
  37. + (if the L5 is in the cache heirarchy).
  38. + 1000 - vector prefetch L1, fetch data as if for a normal scalar load
  39. + but place the cache-line into vector buffer (vector L1) ,
  40. + and imply load into all lower cache destination levels.
  41. +*/
  42. +
  43. +static bfd_boolean check_pref_type(unsigned long type)
  44. +{
  45. + if (type != 0 && type != 1 && type != 2 && type != 3 && type != 8)
  46. + as_bad (_("Improper pref type (%lu)"), type);
  47. +}
  48. +
  49. static symbolS *
  50. make_internal_label (void)
  51. {
  52. @@ -2850,6 +2873,25 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
  53. asarg = expr_end;
  54. continue;
  55. + case '#':
  56. + my_getExpression (imm_expr, asarg);
  57. + check_pref_type((unsigned long)imm_expr->X_add_number);
  58. + INSERT_OPERAND (PREF_TYPE, *ip, imm_expr->X_add_number);
  59. + imm_expr->X_op = O_absent;
  60. + asarg = expr_end;
  61. + continue;
  62. +
  63. + case '+':
  64. + my_getExpression (imm_expr, asarg);
  65. + check_absolute_expr (ip, imm_expr, FALSE);
  66. + if (imm_expr->X_add_number > 127 || imm_expr->X_add_number < -128)
  67. + as_bad (_("Improper pref offset value (%d)"),
  68. + (long) imm_expr->X_add_number);
  69. + INSERT_OPERAND (PREF_OFFSET, *ip, imm_expr->X_add_number);
  70. + imm_expr->X_op = O_absent;
  71. + asarg = expr_end;
  72. + continue;
  73. +
  74. case 'E': /* Control register. */
  75. insn_with_csr = true;
  76. explicit_priv_attr = true;
  77. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  78. index 3eea33a5da..d8635b6fc3 100644
  79. --- a/include/opcode/riscv-opc.h
  80. +++ b/include/opcode/riscv-opc.h
  81. @@ -255,6 +255,7 @@
  82. #define MASK_SFENCE_VMA 0xfe007fff
  83. #define MATCH_WFI 0x10500073
  84. #define MASK_WFI 0xffffffff
  85. +#define MASK_CUSTOMER_PREF 0x7fff
  86. #define MATCH_CSRRW 0x1073
  87. #define MASK_CSRRW 0x707f
  88. #define MATCH_CSRRS 0x2073
  89. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
  90. index b769769b4e..d748e271e6 100644
  91. --- a/include/opcode/riscv.h
  92. +++ b/include/opcode/riscv.h
  93. @@ -156,6 +156,10 @@ static const char * const riscv_pred_succ[16] =
  94. (RV_X(x, 0, 10) << 20)
  95. #define ENCODE_RVV_VC_IMM(x) \
  96. (RV_X(x, 0, 11) << 20)
  97. +#define ENCODE_PREF_TIMM(x) \
  98. + (RV_X(x, 0, 4) << 20)
  99. +#define ENCODE_PREF_SIMM(x) \
  100. + (RV_X(x, 0, 8) << 24)
  101. #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
  102. #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
  103. @@ -256,6 +260,11 @@ static const char * const riscv_pred_succ[16] =
  104. #define OP_MASK_FUNCT2 0x3
  105. #define OP_SH_FUNCT2 25
  106. +#define OP_MASK_PREF_TYPE 0x0f
  107. +#define OP_SH_PREF_TYPE 20
  108. +#define OP_MASK_PREF_OFFSET 0xff
  109. +#define OP_SH_PREF_OFFSET 24
  110. +
  111. /* RVC fields. */
  112. #define OP_MASK_OP2 0x3
  113. diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
  114. index 57b798d8e1..68ba1ee103 100644
  115. --- a/opcodes/riscv-dis.c
  116. +++ b/opcodes/riscv-dis.c
  117. @@ -464,6 +464,13 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
  118. print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l));
  119. break;
  120. + case '#':
  121. + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (PREF_TYPE, l));
  122. + break;
  123. +
  124. + case '+':
  125. + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (PREF_OFFSET, l));
  126. +
  127. case 'S':
  128. case 'U':
  129. print (info->stream, "%s", riscv_fpr_names[rs1]);
  130. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  131. index 523d165226..3704461a4a 100644
  132. --- a/opcodes/riscv-opc.c
  133. +++ b/opcodes/riscv-opc.c
  134. @@ -401,6 +401,7 @@ const struct riscv_opcode riscv_opcodes[] =
  135. {"snez", 0, INSN_CLASS_I, "d,t", MATCH_SLTU, MASK_SLTU|MASK_RS1, match_opcode, INSN_ALIAS },
  136. {"sltz", 0, INSN_CLASS_I, "d,s", MATCH_SLT, MASK_SLT|MASK_RS2, match_opcode, INSN_ALIAS },
  137. {"sgtz", 0, INSN_CLASS_I, "d,t", MATCH_SLT, MASK_SLT|MASK_RS1, match_opcode, INSN_ALIAS },
  138. +{"pref", 0, INSN_CLASS_I, "#,+(s)", MATCH_SLTI, MASK_CUSTOMER_PREF, match_opcode, INSN_ALIAS },
  139. {"slti", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
  140. {"slt", 0, INSN_CLASS_I, "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 },
  141. {"slt", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
  142. --
  143. 2.25.1