0003-add-pref-instruction.patch 5.6 KB

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  1. From 3339a8b15327d7d7bafdf08aad66056fa9ab36b3 Mon Sep 17 00:00:00 2001
  2. From: "max.ma" <max.ma@starfivetech.com>
  3. Date: Sun, 7 Nov 2021 23:01:41 -0800
  4. Subject: [PATCH 3/3] add pref instruction
  5. ---
  6. .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 18 ++++++++++++
  7. .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 2 ++
  8. llvm/lib/Target/RISCV/RISCVInstrFormats.td | 16 +++++++++++
  9. llvm/lib/Target/RISCV/RISCVInstrInfo.td | 28 +++++++++++++++++++
  10. 4 files changed, 64 insertions(+)
  11. diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  12. index 14e67bb8c6c9..a9861d7913cb 100644
  13. --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  14. +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  15. @@ -523,6 +523,15 @@ public:
  16. return IsConstantImm && isUInt<3>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
  17. }
  18. + bool isUImm4() const {
  19. + int64_t Imm;
  20. + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
  21. + if (!isImm())
  22. + return false;
  23. + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
  24. + return IsConstantImm && isUInt<4>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
  25. + }
  26. +
  27. bool isUImm5() const {
  28. int64_t Imm;
  29. RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
  30. @@ -569,6 +578,15 @@ public:
  31. VK == RISCVMCExpr::VK_RISCV_None;
  32. }
  33. + bool isSImm8() const {
  34. + if (!isImm())
  35. + return false;
  36. + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
  37. + int64_t Imm;
  38. + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
  39. + return IsConstantImm && isInt<8>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
  40. + }
  41. +
  42. bool isCLUIImm() const {
  43. if (!isImm())
  44. return false;
  45. diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  46. index ed85e6fa3f24..b4cb7634b7af 100644
  47. --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  48. +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  49. @@ -171,9 +171,11 @@ enum OperandType : unsigned {
  50. OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
  51. OPERAND_UIMM3,
  52. OPERAND_UIMM4,
  53. + OPERAND_UIMM4_PREF,
  54. OPERAND_UIMM5,
  55. OPERAND_UIMM7,
  56. OPERAND_UIMM12,
  57. + OPERAND_SIMM8,
  58. OPERAND_SIMM12,
  59. OPERAND_UIMM20,
  60. OPERAND_UIMMLOG2XLEN,
  61. diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
  62. index d82e414a3f98..7e8e04c50d7a 100644
  63. --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
  64. +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
  65. @@ -334,6 +334,22 @@ class RVInstCache<bits<12> cache, RISCVOpcode opcode, dag outs, dag ins,
  66. let Opcode = opcode.Value;
  67. }
  68. +class RVInstPref<RISCVOpcode opcode, dag outs, dag ins,
  69. + string opcodestr, string argstr>
  70. + : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
  71. +
  72. + bits<8> imm8;
  73. + bits<4> imm4;
  74. + bits<5> rs1;
  75. +
  76. + let Inst{31-24} = imm8;
  77. + let Inst{23-20} = imm4;
  78. + let Inst{19-15} = rs1;
  79. + let Inst{14-12} = 2;
  80. + let Inst{11-7} = 0;
  81. + let Opcode = opcode.Value;
  82. +}
  83. +
  84. class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
  85. dag outs, dag ins, string opcodestr, string argstr>
  86. : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
  87. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
  88. index ea009dc98101..9850f10913f4 100644
  89. --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
  90. +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
  91. @@ -167,6 +167,18 @@ def uimm3 : Operand<XLenVT> {
  92. let OperandNamespace = "RISCVOp";
  93. }
  94. +def uimm4_pref : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<4>(Imm);}]> {
  95. + let ParserMatchClass = UImmAsmOperand<4>;
  96. + let DecoderMethod = "decodeUImmOperand<4>";
  97. + let MCOperandPredicate = [{
  98. + int64_t Imm;
  99. + if (MCOp.evaluateAsConstantImm(Imm))
  100. + return isUInt<4>(Imm) && (imm == 0 || imm == 1 || imm == 2 || imm == 4 || imm == 8);
  101. + }];
  102. + let OperandType = "OPERAND_UIMM4_PREF";
  103. + let OperandNamespace = "RISCVOp";
  104. +}
  105. +
  106. def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
  107. let ParserMatchClass = UImmAsmOperand<5>;
  108. let DecoderMethod = "decodeUImmOperand<5>";
  109. @@ -181,6 +193,14 @@ def uimm7 : Operand<XLenVT> {
  110. let OperandNamespace = "RISCVOp";
  111. }
  112. +def simm8 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<8>(Imm);}]> {
  113. + let ParserMatchClass = SImmAsmOperand<8>;
  114. + let EncoderMethod = "getImmOpValue";
  115. + let DecoderMethod = "decodeSImmOperand<8>";
  116. + let OperandType = "OPERAND_SIMM8";
  117. + let OperandNamespace = "RISCVOp";
  118. +}
  119. +
  120. def simm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<12>(Imm);}]> {
  121. let ParserMatchClass = SImmAsmOperand<12>;
  122. let EncoderMethod = "getImmOpValue";
  123. @@ -452,6 +472,12 @@ class CSR_cache<bits<12> cache, string opcodestr>
  124. : RVInstCache<cache, OPC_SYSTEM, (outs), (ins GPR:$rs1),
  125. opcodestr, "$rs1">, Sched<[WriteCSR, ReadCSR]>;
  126. +let hasNoSchedulingInfo = 1,
  127. + hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
  128. +class PREF_iir<string opcodestr>
  129. + : RVInstPref<OPC_OP_IMM, (outs), (ins uimm4_pref:$imm4, simm8:$imm8, GPR:$rs1),
  130. + opcodestr, "$imm4, ${imm8}(${rs1})">;
  131. +
  132. let hasNoSchedulingInfo = 1,
  133. hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
  134. class CSR_ii<bits<3> funct3, string opcodestr>
  135. @@ -599,6 +625,8 @@ def CFLUSH_D_L1 : CSR_cache<0b111111000000, "cflush.d.l1">;
  136. def CDISCARD_D_L1 : CSR_cache<0b111111000010, "cdiscard.d.l1">;
  137. def CFLUSH_D_L2 : CSR_cache<0b111111000100, "cflush.d.l2">;
  138. def CDISCARD_D_L2 : CSR_cache<0b111111000110, "cdiscard.d.l2">;
  139. +def PREF : PREF_iir<"pref">;
  140. +
  141. /* End */
  142. def CSRRW : CSR_ir<0b001, "csrrw">;
  143. --
  144. 2.33.1