0028-define-__riscv_vector-macro.patch 1.9 KB

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  1. From 730b8fa4b7f04a53ce20e48ff205f638dc9a6ae4 Mon Sep 17 00:00:00 2001
  2. From: "max.ma" <max.ma@starfivetech.com>
  3. Date: Sun, 26 Dec 2021 21:28:53 -0800
  4. Subject: [PATCH 28/32] define __riscv_vector macro
  5. ---
  6. gcc/common/config/riscv/riscv-common.c | 1 +
  7. gcc/config/riscv/riscv-c.c | 3 +++
  8. gcc/config/riscv/riscv.opt | 2 ++
  9. 3 files changed, 6 insertions(+)
  10. diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
  11. index 0927554d506..ce0664a6d08 100644
  12. --- a/gcc/common/config/riscv/riscv-common.c
  13. +++ b/gcc/common/config/riscv/riscv-common.c
  14. @@ -908,6 +908,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
  15. {"f", &gcc_options::x_target_flags, MASK_HARD_FLOAT},
  16. {"d", &gcc_options::x_target_flags, MASK_DOUBLE_FLOAT},
  17. {"c", &gcc_options::x_target_flags, MASK_RVC},
  18. + {"v", &gcc_options::x_target_flags, MASK_VECTOR},
  19. {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
  20. {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
  21. diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c
  22. index efd4a61ea29..44fbeaeb4b5 100644
  23. --- a/gcc/config/riscv/riscv-c.c
  24. +++ b/gcc/config/riscv/riscv-c.c
  25. @@ -54,6 +54,9 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
  26. if (TARGET_DIV && TARGET_MUL)
  27. builtin_define ("__riscv_muldiv");
  28. + if (TARGET_VECTOR)
  29. + builtin_define ("__riscv_vector");
  30. +
  31. builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8);
  32. if (TARGET_HARD_FLOAT)
  33. builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
  34. diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
  35. index 7f7e1c4f50b..3b7d5b591e6 100644
  36. --- a/gcc/config/riscv/riscv.opt
  37. +++ b/gcc/config/riscv/riscv.opt
  38. @@ -146,6 +146,8 @@ Mask(RVC)
  39. Mask(RVE)
  40. +Mask(VECTOR)
  41. +
  42. mriscv-attribute
  43. Target Var(riscv_emit_attribute_p) Init(-1)
  44. Emit RISC-V ELF attribute.
  45. --
  46. 2.33.1