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- From 4ecb7207eb15ac1a955cd6333d24bf7eecd33213 Mon Sep 17 00:00:00 2001
- From: "yilun.xie" <yilun.xie@starfivetech.com>
- Date: Tue, 23 Nov 2021 13:55:44 +0800
- Subject: [PATCH 26/26] RISC-V: bitmanip: fix constant-loading for (1ULL << 31)
- in DImode
- ---
- gcc/config/riscv/riscv.h | 11 ++++-------
- 1 file changed, 4 insertions(+), 7 deletions(-)
- diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
- index ff6729aedac..27ecc4830b2 100644
- --- a/gcc/config/riscv/riscv.h
- +++ b/gcc/config/riscv/riscv.h
- @@ -521,13 +521,10 @@ enum reg_class
- (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \
- || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
-
- -/* If this is a single bit mask, then we can load it with bseti. But this
- - is not useful for any of the low 31 bits because we can use addi or lui
- - to load them. It is wrong for loading SImode 0x80000000 on rv64 because it
- - needs to be sign-extended. So we restrict this to the upper 32-bits
- - only. */
- -#define SINGLE_BIT_MASK_OPERAND(VALUE) \
- - (pow2p_hwi (VALUE) && (ctz_hwi (VALUE) >= 32))
- +/* If this is a single bit mask, then we can load it with bseti. Special
- + handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */
- +#define SINGLE_BIT_MASK_OPERAND(VALUE) \
- + (pow2p_hwi (VALUE))
-
- /* Stack layout; function entry, exit and calling. */
-
- --
- 2.33.1
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