0026-RISC-V-bitmanip-fix-constant-loading-for-1ULL-31-in-.patch 1.4 KB

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  1. From 4ecb7207eb15ac1a955cd6333d24bf7eecd33213 Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Tue, 23 Nov 2021 13:55:44 +0800
  4. Subject: [PATCH 26/26] RISC-V: bitmanip: fix constant-loading for (1ULL << 31)
  5. in DImode
  6. ---
  7. gcc/config/riscv/riscv.h | 11 ++++-------
  8. 1 file changed, 4 insertions(+), 7 deletions(-)
  9. diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
  10. index ff6729aedac..27ecc4830b2 100644
  11. --- a/gcc/config/riscv/riscv.h
  12. +++ b/gcc/config/riscv/riscv.h
  13. @@ -521,13 +521,10 @@ enum reg_class
  14. (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \
  15. || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
  16. -/* If this is a single bit mask, then we can load it with bseti. But this
  17. - is not useful for any of the low 31 bits because we can use addi or lui
  18. - to load them. It is wrong for loading SImode 0x80000000 on rv64 because it
  19. - needs to be sign-extended. So we restrict this to the upper 32-bits
  20. - only. */
  21. -#define SINGLE_BIT_MASK_OPERAND(VALUE) \
  22. - (pow2p_hwi (VALUE) && (ctz_hwi (VALUE) >= 32))
  23. +/* If this is a single bit mask, then we can load it with bseti. Special
  24. + handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */
  25. +#define SINGLE_BIT_MASK_OPERAND(VALUE) \
  26. + (pow2p_hwi (VALUE))
  27. /* Stack layout; function entry, exit and calling. */
  28. --
  29. 2.33.1