0019-Implement-instruction-patterns-for-ZBB-extension.patch 8.5 KB

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  1. From adb47e7bb51c1725f36b9b92ba5b0bd2f7a1d74d Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Thu, 18 Nov 2021 15:16:54 +0800
  4. Subject: [PATCH 19/26] Implement instruction patterns for ZBB extension
  5. ---
  6. gcc/config/riscv/riscv.md | 21 ++++++++++---
  7. .../gcc.target/riscv/zbb-andn-orn-xnor-01.c | 21 +++++++++++++
  8. .../gcc.target/riscv/zbb-andn-orn-xnor-02.c | 21 +++++++++++++
  9. gcc/testsuite/gcc.target/riscv/zbb-min-max.c | 31 +++++++++++++++++++
  10. .../gcc.target/riscv/zbb-rol-ror-01.c | 16 ++++++++++
  11. .../gcc.target/riscv/zbb-rol-ror-02.c | 16 ++++++++++
  12. .../gcc.target/riscv/zbb-rol-ror-03.c | 17 ++++++++++
  13. gcc/testsuite/gcc.target/riscv/zbbw.c | 25 +++++++++++++++
  14. 8 files changed, 163 insertions(+), 5 deletions(-)
  15. create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
  16. create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
  17. create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-min-max.c
  18. create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
  19. create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
  20. create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
  21. create mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c
  22. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
  23. index 34702af3aff..143a83eec83 100644
  24. --- a/gcc/config/riscv/riscv.md
  25. +++ b/gcc/config/riscv/riscv.md
  26. @@ -170,7 +170,7 @@
  27. (define_attr "type"
  28. "unknown,branch,jump,call,load,fpload,store,fpstore,
  29. mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
  30. - fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip"
  31. + fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate"
  32. (cond [(eq_attr "got" "load") (const_string "load")
  33. ;; If a doubleword move uses these expensive instructions,
  34. @@ -1081,11 +1081,17 @@
  35. [(set_attr "move_type" "shift_shift,load")
  36. (set_attr "mode" "DI")])
  37. -(define_insn_and_split "zero_extendhi<GPR:mode>2"
  38. +(define_expand "zero_extendhi<GPR:mode>2"
  39. + [(set (match_operand:GPR 0 "register_operand")
  40. + (zero_extend:GPR
  41. + (match_operand:HI 1 "nonimmediate_operand")))]
  42. + "")
  43. +
  44. +(define_insn_and_split "*zero_extendhi<GPR:mode>2"
  45. [(set (match_operand:GPR 0 "register_operand" "=r,r")
  46. (zero_extend:GPR
  47. (match_operand:HI 1 "nonimmediate_operand" " r,m")))]
  48. - ""
  49. + "!TARGET_ZBB"
  50. "@
  51. #
  52. lhu\t%0,%1"
  53. @@ -1132,11 +1138,16 @@
  54. [(set_attr "move_type" "move,load")
  55. (set_attr "mode" "DI")])
  56. -(define_insn_and_split "extend<SHORT:mode><SUPERQI:mode>2"
  57. +(define_expand "extend<SHORT:mode><SUPERQI:mode>2"
  58. + [(set (match_operand:SUPERQI 0 "register_operand")
  59. + (sign_extend:SUPERQI (match_operand:SHORT 1 "nonimmediate_operand")))]
  60. + "")
  61. +
  62. +(define_insn_and_split "*extend<SHORT:mode><SUPERQI:mode>2"
  63. [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
  64. (sign_extend:SUPERQI
  65. (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
  66. - ""
  67. + "!TARGET_ZBB"
  68. "@
  69. #
  70. l<SHORT:size>\t%0,%1"
  71. diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
  72. new file mode 100644
  73. index 00000000000..0037dea5647
  74. --- /dev/null
  75. +++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
  76. @@ -0,0 +1,21 @@
  77. +/* { dg-do compile } */
  78. +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
  79. +
  80. +unsigned long long foo1(unsigned long long rs1, unsigned long long rs2)
  81. +{
  82. +return rs1 & ~rs2;
  83. +}
  84. +
  85. +unsigned long long foo2(unsigned long long rs1, unsigned long long rs2)
  86. +{
  87. +return rs1 | ~rs2;
  88. +}
  89. +
  90. +unsigned long long foo3(unsigned long long rs1, unsigned long long rs2)
  91. +{
  92. +return rs1 ^ ~rs2;
  93. +}
  94. +
  95. +/* { dg-final { scan-assembler-times "andn" 2 } } */
  96. +/* { dg-final { scan-assembler-times "orn" 2 } } */
  97. +/* { dg-final { scan-assembler-times "xnor" 2 } } */
  98. \ No newline at end of file
  99. diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
  100. new file mode 100644
  101. index 00000000000..b0c1e40c554
  102. --- /dev/null
  103. +++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
  104. @@ -0,0 +1,21 @@
  105. +/* { dg-do compile } */
  106. +/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
  107. +
  108. +unsigned int foo1(unsigned int rs1, unsigned int rs2)
  109. +{
  110. +return rs1 & ~rs2;
  111. +}
  112. +
  113. +unsigned int foo2(unsigned int rs1, unsigned int rs2)
  114. +{
  115. +return rs1 | ~rs2;
  116. +}
  117. +
  118. +unsigned int foo3(unsigned int rs1, unsigned int rs2)
  119. +{
  120. +return rs1 ^ ~rs2;
  121. +}
  122. +
  123. +/* { dg-final { scan-assembler-times "andn" 2 } } */
  124. +/* { dg-final { scan-assembler-times "orn" 2 } } */
  125. +/* { dg-final { scan-assembler-times "xnor" 2 } } */
  126. \ No newline at end of file
  127. diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
  128. new file mode 100644
  129. index 00000000000..dc72bb4ad71
  130. --- /dev/null
  131. +++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
  132. @@ -0,0 +1,31 @@
  133. +/* { dg-do compile } */
  134. +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
  135. +
  136. +long
  137. +foo1 (long i, long j)
  138. +{
  139. + return i < j ? i : j;
  140. +}
  141. +
  142. +long
  143. +foo2 (long i, long j)
  144. +{
  145. + return i > j ? i : j;
  146. +}
  147. +
  148. +unsigned long
  149. +foo3 (unsigned long i, unsigned long j)
  150. +{
  151. + return i < j ? i : j;
  152. +}
  153. +
  154. +unsigned long
  155. +foo4 (unsigned long i, unsigned long j)
  156. +{
  157. + return i > j ? i : j;
  158. +}
  159. +
  160. +/* { dg-final { scan-assembler-times "min" 3 } } */
  161. +/* { dg-final { scan-assembler-times "max" 3 } } */
  162. +/* { dg-final { scan-assembler-times "minu" 1 } } */
  163. +/* { dg-final { scan-assembler-times "maxu" 1 } } */
  164. \ No newline at end of file
  165. diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
  166. new file mode 100644
  167. index 00000000000..958966289df
  168. --- /dev/null
  169. +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
  170. @@ -0,0 +1,16 @@
  171. +/* { dg-do compile } */
  172. +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
  173. +
  174. +unsigned long foo1(unsigned long rs1, unsigned long rs2)
  175. +{
  176. + long shamt = rs2 & (64 - 1);
  177. + return (rs1 << shamt) | (rs1 >> ((64 - shamt) & (64 - 1)));
  178. +}
  179. +unsigned long foo2(unsigned long rs1, unsigned long rs2)
  180. +{
  181. + unsigned long shamt = rs2 & (64 - 1);
  182. + return (rs1 >> shamt) | (rs1 << ((64 - shamt) & (64 - 1)));
  183. +}
  184. +
  185. +/* { dg-final { scan-assembler-times "rol" 2 } } */
  186. +/* { dg-final { scan-assembler-times "ror" 2 } } */
  187. \ No newline at end of file
  188. diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
  189. new file mode 100644
  190. index 00000000000..24b482f2145
  191. --- /dev/null
  192. +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
  193. @@ -0,0 +1,16 @@
  194. +/* { dg-do compile } */
  195. +/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
  196. +
  197. +unsigned int foo1(unsigned int rs1, unsigned int rs2)
  198. +{
  199. + unsigned int shamt = rs2 & (32 - 1);
  200. + return (rs1 << shamt) | (rs1 >> ((32 - shamt) & (32 - 1)));
  201. +}
  202. +unsigned int foo2(unsigned int rs1, unsigned int rs2)
  203. +{
  204. + unsigned int shamt = rs2 & (32 - 1);
  205. + return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1)));
  206. +}
  207. +
  208. +/* { dg-final { scan-assembler-times "rol" 2 } } */
  209. +/* { dg-final { scan-assembler-times "ror" 2 } } */
  210. \ No newline at end of file
  211. diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
  212. new file mode 100644
  213. index 00000000000..ffde7c9cd58
  214. --- /dev/null
  215. +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
  216. @@ -0,0 +1,17 @@
  217. +/* { dg-do compile } */
  218. +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
  219. +
  220. +/* RV64 only*/
  221. +unsigned int rol(unsigned int rs1, unsigned int rs2)
  222. +{
  223. + int shamt = rs2 & (32 - 1);
  224. + return (rs1 << shamt) | (rs1 >> ((64 - shamt) & (32 - 1)));
  225. +}
  226. +unsigned int ror(unsigned int rs1, unsigned int rs2)
  227. +{
  228. + int shamt = rs2 & (64 - 1);
  229. + return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1)));
  230. +}
  231. +
  232. +/* { dg-final { scan-assembler-times "rolw" 1 } } */
  233. +/* { dg-final { scan-assembler-times "rorw" 1 } } */
  234. \ No newline at end of file
  235. diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c
  236. new file mode 100644
  237. index 00000000000..ed88ca5cceb
  238. --- /dev/null
  239. +++ b/gcc/testsuite/gcc.target/riscv/zbbw.c
  240. @@ -0,0 +1,25 @@
  241. +/* { dg-do compile } */
  242. +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
  243. +
  244. +int
  245. +clz (int i)
  246. +{
  247. + return __builtin_clz (i);
  248. +}
  249. +
  250. +int
  251. +ctz (int i)
  252. +{
  253. + return __builtin_ctz (i);
  254. +}
  255. +
  256. +int
  257. +popcount (int i)
  258. +{
  259. + return __builtin_popcount (i);
  260. +}
  261. +
  262. +
  263. +/* { dg-final { scan-assembler-times "clzw" 1 } } */
  264. +/* { dg-final { scan-assembler-times "ctzw" 1 } } */
  265. +/* { dg-final { scan-assembler-times "cpopw" 1 } } */
  266. \ No newline at end of file
  267. --
  268. 2.33.1