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- From adb47e7bb51c1725f36b9b92ba5b0bd2f7a1d74d Mon Sep 17 00:00:00 2001
- From: "yilun.xie" <yilun.xie@starfivetech.com>
- Date: Thu, 18 Nov 2021 15:16:54 +0800
- Subject: [PATCH 19/26] Implement instruction patterns for ZBB extension
- ---
- gcc/config/riscv/riscv.md | 21 ++++++++++---
- .../gcc.target/riscv/zbb-andn-orn-xnor-01.c | 21 +++++++++++++
- .../gcc.target/riscv/zbb-andn-orn-xnor-02.c | 21 +++++++++++++
- gcc/testsuite/gcc.target/riscv/zbb-min-max.c | 31 +++++++++++++++++++
- .../gcc.target/riscv/zbb-rol-ror-01.c | 16 ++++++++++
- .../gcc.target/riscv/zbb-rol-ror-02.c | 16 ++++++++++
- .../gcc.target/riscv/zbb-rol-ror-03.c | 17 ++++++++++
- gcc/testsuite/gcc.target/riscv/zbbw.c | 25 +++++++++++++++
- 8 files changed, 163 insertions(+), 5 deletions(-)
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-min-max.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c
- diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
- index 34702af3aff..143a83eec83 100644
- --- a/gcc/config/riscv/riscv.md
- +++ b/gcc/config/riscv/riscv.md
- @@ -170,7 +170,7 @@
- (define_attr "type"
- "unknown,branch,jump,call,load,fpload,store,fpstore,
- mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
- - fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip"
- + fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate"
- (cond [(eq_attr "got" "load") (const_string "load")
-
- ;; If a doubleword move uses these expensive instructions,
- @@ -1081,11 +1081,17 @@
- [(set_attr "move_type" "shift_shift,load")
- (set_attr "mode" "DI")])
-
- -(define_insn_and_split "zero_extendhi<GPR:mode>2"
- +(define_expand "zero_extendhi<GPR:mode>2"
- + [(set (match_operand:GPR 0 "register_operand")
- + (zero_extend:GPR
- + (match_operand:HI 1 "nonimmediate_operand")))]
- + "")
- +
- +(define_insn_and_split "*zero_extendhi<GPR:mode>2"
- [(set (match_operand:GPR 0 "register_operand" "=r,r")
- (zero_extend:GPR
- (match_operand:HI 1 "nonimmediate_operand" " r,m")))]
- - ""
- + "!TARGET_ZBB"
- "@
- #
- lhu\t%0,%1"
- @@ -1132,11 +1138,16 @@
- [(set_attr "move_type" "move,load")
- (set_attr "mode" "DI")])
-
- -(define_insn_and_split "extend<SHORT:mode><SUPERQI:mode>2"
- +(define_expand "extend<SHORT:mode><SUPERQI:mode>2"
- + [(set (match_operand:SUPERQI 0 "register_operand")
- + (sign_extend:SUPERQI (match_operand:SHORT 1 "nonimmediate_operand")))]
- + "")
- +
- +(define_insn_and_split "*extend<SHORT:mode><SUPERQI:mode>2"
- [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
- (sign_extend:SUPERQI
- (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
- - ""
- + "!TARGET_ZBB"
- "@
- #
- l<SHORT:size>\t%0,%1"
- diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
- new file mode 100644
- index 00000000000..0037dea5647
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
- @@ -0,0 +1,21 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
- +
- +unsigned long long foo1(unsigned long long rs1, unsigned long long rs2)
- +{
- +return rs1 & ~rs2;
- +}
- +
- +unsigned long long foo2(unsigned long long rs1, unsigned long long rs2)
- +{
- +return rs1 | ~rs2;
- +}
- +
- +unsigned long long foo3(unsigned long long rs1, unsigned long long rs2)
- +{
- +return rs1 ^ ~rs2;
- +}
- +
- +/* { dg-final { scan-assembler-times "andn" 2 } } */
- +/* { dg-final { scan-assembler-times "orn" 2 } } */
- +/* { dg-final { scan-assembler-times "xnor" 2 } } */
- \ No newline at end of file
- diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
- new file mode 100644
- index 00000000000..b0c1e40c554
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
- @@ -0,0 +1,21 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
- +
- +unsigned int foo1(unsigned int rs1, unsigned int rs2)
- +{
- +return rs1 & ~rs2;
- +}
- +
- +unsigned int foo2(unsigned int rs1, unsigned int rs2)
- +{
- +return rs1 | ~rs2;
- +}
- +
- +unsigned int foo3(unsigned int rs1, unsigned int rs2)
- +{
- +return rs1 ^ ~rs2;
- +}
- +
- +/* { dg-final { scan-assembler-times "andn" 2 } } */
- +/* { dg-final { scan-assembler-times "orn" 2 } } */
- +/* { dg-final { scan-assembler-times "xnor" 2 } } */
- \ No newline at end of file
- diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
- new file mode 100644
- index 00000000000..dc72bb4ad71
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
- @@ -0,0 +1,31 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
- +
- +long
- +foo1 (long i, long j)
- +{
- + return i < j ? i : j;
- +}
- +
- +long
- +foo2 (long i, long j)
- +{
- + return i > j ? i : j;
- +}
- +
- +unsigned long
- +foo3 (unsigned long i, unsigned long j)
- +{
- + return i < j ? i : j;
- +}
- +
- +unsigned long
- +foo4 (unsigned long i, unsigned long j)
- +{
- + return i > j ? i : j;
- +}
- +
- +/* { dg-final { scan-assembler-times "min" 3 } } */
- +/* { dg-final { scan-assembler-times "max" 3 } } */
- +/* { dg-final { scan-assembler-times "minu" 1 } } */
- +/* { dg-final { scan-assembler-times "maxu" 1 } } */
- \ No newline at end of file
- diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
- new file mode 100644
- index 00000000000..958966289df
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
- @@ -0,0 +1,16 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
- +
- +unsigned long foo1(unsigned long rs1, unsigned long rs2)
- +{
- + long shamt = rs2 & (64 - 1);
- + return (rs1 << shamt) | (rs1 >> ((64 - shamt) & (64 - 1)));
- +}
- +unsigned long foo2(unsigned long rs1, unsigned long rs2)
- +{
- + unsigned long shamt = rs2 & (64 - 1);
- + return (rs1 >> shamt) | (rs1 << ((64 - shamt) & (64 - 1)));
- +}
- +
- +/* { dg-final { scan-assembler-times "rol" 2 } } */
- +/* { dg-final { scan-assembler-times "ror" 2 } } */
- \ No newline at end of file
- diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
- new file mode 100644
- index 00000000000..24b482f2145
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
- @@ -0,0 +1,16 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
- +
- +unsigned int foo1(unsigned int rs1, unsigned int rs2)
- +{
- + unsigned int shamt = rs2 & (32 - 1);
- + return (rs1 << shamt) | (rs1 >> ((32 - shamt) & (32 - 1)));
- +}
- +unsigned int foo2(unsigned int rs1, unsigned int rs2)
- +{
- + unsigned int shamt = rs2 & (32 - 1);
- + return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1)));
- +}
- +
- +/* { dg-final { scan-assembler-times "rol" 2 } } */
- +/* { dg-final { scan-assembler-times "ror" 2 } } */
- \ No newline at end of file
- diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
- new file mode 100644
- index 00000000000..ffde7c9cd58
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
- @@ -0,0 +1,17 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
- +
- +/* RV64 only*/
- +unsigned int rol(unsigned int rs1, unsigned int rs2)
- +{
- + int shamt = rs2 & (32 - 1);
- + return (rs1 << shamt) | (rs1 >> ((64 - shamt) & (32 - 1)));
- +}
- +unsigned int ror(unsigned int rs1, unsigned int rs2)
- +{
- + int shamt = rs2 & (64 - 1);
- + return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1)));
- +}
- +
- +/* { dg-final { scan-assembler-times "rolw" 1 } } */
- +/* { dg-final { scan-assembler-times "rorw" 1 } } */
- \ No newline at end of file
- diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c
- new file mode 100644
- index 00000000000..ed88ca5cceb
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zbbw.c
- @@ -0,0 +1,25 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
- +
- +int
- +clz (int i)
- +{
- + return __builtin_clz (i);
- +}
- +
- +int
- +ctz (int i)
- +{
- + return __builtin_ctz (i);
- +}
- +
- +int
- +popcount (int i)
- +{
- + return __builtin_popcount (i);
- +}
- +
- +
- +/* { dg-final { scan-assembler-times "clzw" 1 } } */
- +/* { dg-final { scan-assembler-times "ctzw" 1 } } */
- +/* { dg-final { scan-assembler-times "cpopw" 1 } } */
- \ No newline at end of file
- --
- 2.33.1
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