0018-Cost-model-for-zba-extension.patch 3.7 KB

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  1. From b58a42aac28becb118a8482d41c4188e00ad0c3a Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Thu, 18 Nov 2021 14:55:04 +0800
  4. Subject: [PATCH 18/26] Cost model for zba extension
  5. ---
  6. gcc/config/riscv/riscv.c | 82 ++++++++++++++++++++++++++++++++++++++++
  7. 1 file changed, 82 insertions(+)
  8. diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
  9. index 17cdf705c32..7d5e22d9fe2 100644
  10. --- a/gcc/config/riscv/riscv.c
  11. +++ b/gcc/config/riscv/riscv.c
  12. @@ -1680,6 +1680,10 @@ riscv_extend_cost (rtx op, bool unsigned_p)
  13. /* We can use ANDI. */
  14. return COSTS_N_INSNS (1);
  15. + /* ZBA provide zext.w. */
  16. + if (TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE (op) == SImode)
  17. + return COSTS_N_INSNS (1);
  18. +
  19. if (!unsigned_p && GET_MODE (op) == SImode)
  20. /* We can use SEXT.W. */
  21. return COSTS_N_INSNS (1);
  22. @@ -1753,6 +1757,22 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
  23. return false;
  24. case AND:
  25. + /* slli.uw pattern for zba. */
  26. + if (TARGET_ZBA && TARGET_64BIT && mode == DImode
  27. + && GET_CODE (XEXP (x, 0)) == ASHIFT)
  28. + {
  29. + rtx and_rhs = XEXP (x, 1);
  30. + rtx ashift_lhs = XEXP (XEXP (x, 0), 0);
  31. + rtx ashift_rhs = XEXP (XEXP (x, 0), 1);
  32. + if (REG_P (ashift_lhs)
  33. + && CONST_INT_P (ashift_rhs)
  34. + && CONST_INT_P (and_rhs)
  35. + && ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff))
  36. + *total = COSTS_N_INSNS (1);
  37. + return true;
  38. + }
  39. + gcc_fallthrough ();
  40. +
  41. case IOR:
  42. case XOR:
  43. /* Double-word operations use two single-word operations. */
  44. @@ -1844,6 +1864,68 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
  45. case MINUS:
  46. case PLUS:
  47. + /* add.uw pattern for zba. */
  48. + if (TARGET_ZBA
  49. + && (TARGET_64BIT && (mode == DImode))
  50. + && GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
  51. + && REG_P (XEXP (XEXP (x, 0), 0))
  52. + && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
  53. + {
  54. + *total = COSTS_N_INSNS (1);
  55. + return true;
  56. + }
  57. + /* shNadd pattern for zba. */
  58. + if (TARGET_ZBA
  59. + && ((!TARGET_64BIT && (mode == SImode)) ||
  60. + (TARGET_64BIT && (mode == DImode)))
  61. + && (GET_CODE (XEXP (x, 0)) == ASHIFT)
  62. + && REG_P (XEXP (XEXP (x, 0), 0))
  63. + && CONST_INT_P (XEXP (XEXP (x, 0), 0))
  64. + && IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 0)), 1, 3))
  65. + {
  66. + *total = COSTS_N_INSNS (1);
  67. + return true;
  68. + }
  69. + /* shNadd.uw pattern for zba.
  70. + [(set (match_operand:DI 0 "register_operand" "=r")
  71. + (plus:DI
  72. + (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
  73. + (match_operand:QI 2 "immediate_operand" "I"))
  74. + (match_operand 3 "immediate_operand" ""))
  75. + (match_operand:DI 4 "register_operand" "r")))]
  76. + "TARGET_64BIT && TARGET_ZBA
  77. + && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
  78. + && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
  79. + */
  80. + if (TARGET_ZBA
  81. + && (TARGET_64BIT && (mode == DImode))
  82. + && (GET_CODE (XEXP (x, 0)) == AND)
  83. + && (REG_P (XEXP (x, 1))))
  84. + {
  85. + do {
  86. + rtx and_lhs = XEXP (XEXP (x, 0), 0);
  87. + rtx and_rhs = XEXP (XEXP (x, 0), 1);
  88. + if (GET_CODE (and_lhs) != ASHIFT)
  89. + break;
  90. + if (!CONST_INT_P (and_rhs))
  91. + break;
  92. +
  93. + rtx ashift_lhs = XEXP (and_lhs, 0);
  94. + rtx ashift_rhs = XEXP (and_lhs, 1);
  95. +
  96. + if (!CONST_INT_P (ashift_rhs)
  97. + || !IN_RANGE (INTVAL (ashift_rhs), 1, 3))
  98. + break;
  99. +
  100. + if (CONST_INT_P (and_rhs)
  101. + && ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff))
  102. + {
  103. + *total = COSTS_N_INSNS (1);
  104. + return true;
  105. + }
  106. + } while (false);
  107. + }
  108. +
  109. if (float_mode_p)
  110. *total = tune_param->fp_add[mode == DFmode];
  111. else
  112. --
  113. 2.33.1