0015-add-builtin-orc.b-clmul-clmulr-clmulh.patch 4.7 KB

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  1. From 7b4956f76d1f495d8c7b785c97682a36d852d184 Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Thu, 4 Nov 2021 17:26:53 +0800
  4. Subject: [PATCH 15/15] add builtin orc.b/clmul/clmulr/clmulh
  5. ---
  6. gcc/config/riscv/riscv-builtins.c | 10 ++++++++
  7. gcc/config/riscv/riscv-ftypes.def | 2 ++
  8. gcc/config/riscv/riscv.md | 40 ++++++++++++++++++++++++++++++-
  9. 3 files changed, 51 insertions(+), 1 deletion(-)
  10. diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c
  11. index 97b1480a15e..674e3f6dc04 100644
  12. --- a/gcc/config/riscv/riscv-builtins.c
  13. +++ b/gcc/config/riscv/riscv-builtins.c
  14. @@ -40,6 +40,7 @@ along with GCC; see the file COPYING3. If not see
  15. /* Macros to create an enumeration identifier for a function prototype. */
  16. #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
  17. #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
  18. +#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
  19. /* Classifies the prototype of a built-in function. */
  20. enum riscv_function_type {
  21. @@ -86,6 +87,8 @@ struct riscv_builtin_description {
  22. };
  23. AVAIL (hard_float, TARGET_HARD_FLOAT)
  24. +AVAIL (zbb, TARGET_ZBB)
  25. +AVAIL (zbc, TARGET_ZBC)
  26. /* Construct a riscv_builtin_description from the given arguments.
  27. @@ -119,6 +122,7 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
  28. /* Argument types. */
  29. #define RISCV_ATYPE_VOID void_type_node
  30. #define RISCV_ATYPE_USI unsigned_intSI_type_node
  31. +#define RISCV_ATYPE_SI intSI_type_node
  32. /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
  33. their associated RISCV_ATYPEs. */
  34. @@ -126,8 +130,14 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
  35. RISCV_ATYPE_##A
  36. #define RISCV_FTYPE_ATYPES1(A, B) \
  37. RISCV_ATYPE_##A, RISCV_ATYPE_##B
  38. +#define RISCV_FTYPE_ATYPES2(A, B, C) \
  39. + RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
  40. static const struct riscv_builtin_description riscv_builtins[] = {
  41. + DIRECT_BUILTIN (orc_b, RISCV_SI_FTYPE_SI, zbb),
  42. + DIRECT_BUILTIN (clmul, RISCV_SI_FTYPE_SI_SI, zbc),
  43. + DIRECT_BUILTIN (clmulh, RISCV_SI_FTYPE_SI_SI, zbc),
  44. + DIRECT_BUILTIN (clmulr, RISCV_SI_FTYPE_SI_SI, zbc),
  45. DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
  46. DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float)
  47. };
  48. diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
  49. index b19b731bdf2..ab7348d1d7d 100644
  50. --- a/gcc/config/riscv/riscv-ftypes.def
  51. +++ b/gcc/config/riscv/riscv-ftypes.def
  52. @@ -28,3 +28,5 @@ along with GCC; see the file COPYING3. If not see
  53. DEF_RISCV_FTYPE (0, (USI))
  54. DEF_RISCV_FTYPE (1, (VOID, USI))
  55. +DEF_RISCV_FTYPE (1, (SI, SI))
  56. +DEF_RISCV_FTYPE (2, (SI, SI, SI))
  57. \ No newline at end of file
  58. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
  59. index c3687d57047..26003ac5df7 100644
  60. --- a/gcc/config/riscv/riscv.md
  61. +++ b/gcc/config/riscv/riscv.md
  62. @@ -170,7 +170,7 @@
  63. (define_attr "type"
  64. "unknown,branch,jump,call,load,fpload,store,fpstore,
  65. mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
  66. - fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost"
  67. + fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip"
  68. (cond [(eq_attr "got" "load") (const_string "load")
  69. ;; If a doubleword move uses these expensive instructions,
  70. @@ -2504,6 +2504,44 @@
  71. [(set_attr "length" "0")]
  72. )
  73. +(define_insn "riscv_orc_b"
  74. + [(set (match_operand:SI 0 "register_operand" "=r")
  75. + (sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
  76. + "TARGET_ZBB"
  77. + "orc.b\t%0,%1,%2"
  78. + [(set_attr "type" "bitmanip")])
  79. +
  80. +(define_insn "riscv_rev8"
  81. + [(set (match_operand:SI 0 "register_operand" "=r")
  82. + (sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
  83. + "TARGET_ZBB"
  84. + "rev8\t%0,%1,%2"
  85. + [(set_attr "type" "bitmanip")])
  86. +
  87. +(define_insn "riscv_clmul"
  88. + [(set (match_operand:SI 0 "register_operand" "=r")
  89. + (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  90. + (match_operand:SI 2 "register_operand" "r"))))]
  91. + "TARGET_ZBC"
  92. + "clmul\t%0,%1,%2"
  93. + [(set_attr "type" "bitmanip")])
  94. +
  95. +(define_insn "riscv_clmulh"
  96. + [(set (match_operand:SI 0 "register_operand" "=r")
  97. + (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  98. + (match_operand:SI 2 "register_operand" "r"))))]
  99. + "TARGET_ZBC"
  100. + "clmulh\t%0,%1,%2"
  101. + [(set_attr "type" "bitmanip")])
  102. +
  103. +(define_insn "riscv_clmulr"
  104. + [(set (match_operand:SI 0 "register_operand" "=r")
  105. + (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  106. + (match_operand:SI 2 "register_operand" "r"))))]
  107. + "TARGET_ZBC"
  108. + "clmulr\t%0,%1,%2"
  109. + [(set_attr "type" "bitmanip")])
  110. +
  111. ;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a
  112. ;; 32-bit target when using -mtune=sifive-7-series. The first sched pass
  113. ;; runs before register elimination, and we have a non-obvious dependency
  114. --
  115. 2.33.1