0010-Merge-B-instruction-from-0p94-to-1.0.patch 8.8 KB

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  1. From c1eb999a3aed84d42c792280ea2c313d1c6063ca Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Fri, 22 Oct 2021 16:10:16 +0800
  4. Subject: [PATCH 10/15] Merge B instruction from 0p94 to 1.0
  5. ---
  6. gcc/common/config/riscv/riscv-common.c | 28 +++---------
  7. gcc/config/riscv/bitmanip.md | 62 +++++---------------------
  8. gcc/config/riscv/riscv-opts.h | 14 +-----
  9. 3 files changed, 17 insertions(+), 87 deletions(-)
  10. diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
  11. index 28475fc76b5..48eb558bcf5 100644
  12. --- a/gcc/common/config/riscv/riscv-common.c
  13. +++ b/gcc/common/config/riscv/riscv-common.c
  14. @@ -53,13 +53,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
  15. {"b", "zbb"},
  16. {"b", "zbs"},
  17. {"b", "zba"},
  18. - {"b", "zbp"},
  19. - {"b", "zbe"},
  20. - {"b", "zbf"},
  21. {"b", "zbc"},
  22. - {"b", "zbm"},
  23. - {"b", "zbr"},
  24. - {"b", "zbt"},
  25. {NULL, NULL}
  26. };
  27. @@ -111,17 +105,11 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
  28. {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
  29. {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
  30. - {"b", ISA_SPEC_CLASS_NONE, 0, 94},
  31. - {"zba", ISA_SPEC_CLASS_NONE, 0, 94},
  32. - {"zbb", ISA_SPEC_CLASS_NONE, 0, 94},
  33. - {"zbc", ISA_SPEC_CLASS_NONE, 0, 94},
  34. - {"zbe", ISA_SPEC_CLASS_NONE, 0, 94},
  35. - {"zbf", ISA_SPEC_CLASS_NONE, 0, 94},
  36. - {"zbr", ISA_SPEC_CLASS_NONE, 0, 94},
  37. - {"zbm", ISA_SPEC_CLASS_NONE, 0, 94},
  38. - {"zbs", ISA_SPEC_CLASS_NONE, 0, 94},
  39. - {"zbt", ISA_SPEC_CLASS_NONE, 0, 94},
  40. - {"zbp", ISA_SPEC_CLASS_NONE, 0, 94},
  41. + {"b", ISA_SPEC_CLASS_NONE, 1, 0},
  42. + {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
  43. + {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
  44. + {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
  45. + {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
  46. /* Terminate the list. */
  47. {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
  48. };
  49. @@ -929,13 +917,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
  50. {"zba", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBA},
  51. {"zbb", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBB},
  52. {"zbs", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBS},
  53. - {"zbp", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBP},
  54. - {"zbr", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBR},
  55. - {"zbe", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBE},
  56. - {"zbf", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBF},
  57. {"zbc", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBC},
  58. - {"zbm", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBM},
  59. - {"zbt", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBT},
  60. {NULL, NULL, 0}
  61. };
  62. diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
  63. index 6653219c3f0..ceb5c89dd47 100644
  64. --- a/gcc/config/riscv/bitmanip.md
  65. +++ b/gcc/config/riscv/bitmanip.md
  66. @@ -69,7 +69,7 @@
  67. [(set (match_operand:X 0 "register_operand" "=r")
  68. (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
  69. (match_operand:X 2 "register_operand" "r")))]
  70. - "TARGET_ZBB || TARGET_ZBP"
  71. + "TARGET_ZBB"
  72. "<insn>n\t%0,%2,%1"
  73. [(set_attr "type" "bitmanip")])
  74. @@ -77,7 +77,7 @@
  75. [(set (match_operand:X 0 "register_operand" "=r")
  76. (not:X (xor:X (match_operand:X 1 "register_operand" "r")
  77. (match_operand:X 2 "register_operand" "r"))))]
  78. - "TARGET_ZBB || TARGET_ZBP"
  79. + "TARGET_ZBB"
  80. "xnor\t%0,%1,%2"
  81. [(set_attr "type" "bitmanip")])
  82. @@ -86,7 +86,7 @@
  83. (define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
  84. [(set (match_operand:GPR 0 "register_operand" "=r,r")
  85. (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
  86. - "TARGET_ZBB || TARGET_ZBP"
  87. + "TARGET_ZBB"
  88. "@
  89. zext.h\t%0,%1
  90. lhu\t%0,%1"
  91. @@ -301,7 +301,7 @@
  92. [(set (match_operand:SI 0 "register_operand" "=r")
  93. (rotatert:SI (match_operand:SI 1 "register_operand" "r")
  94. (match_operand:QI 2 "arith_operand" "rI")))]
  95. - "TARGET_ZBB || TARGET_ZBP"
  96. + "TARGET_ZBB"
  97. { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
  98. [(set_attr "type" "bitmanip")])
  99. @@ -309,7 +309,7 @@
  100. [(set (match_operand:DI 0 "register_operand" "=r")
  101. (rotatert:DI (match_operand:DI 1 "register_operand" "r")
  102. (match_operand:QI 2 "arith_operand" "rI")))]
  103. - "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
  104. + "TARGET_64BIT && TARGET_ZBB"
  105. "ror%i2\t%0,%1,%2"
  106. [(set_attr "type" "bitmanip")])
  107. @@ -317,7 +317,7 @@
  108. [(match_operand:SI 0 "register_operand" "=r")
  109. (match_operand:SI 1 "register_operand" "r")
  110. (match_operand:SI 2 "register_operand" "r")]
  111. - "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
  112. + "TARGET_64BIT && TARGET_ZBB"
  113. {
  114. emit_insn (gen_rotlsi3 (operands[0], operands[1], operands[2]));
  115. DONE;
  116. @@ -327,7 +327,7 @@
  117. [(set (match_operand:SI 0 "register_operand" "=r")
  118. (rotate:SI (match_operand:SI 1 "register_operand" "r")
  119. (match_operand:QI 2 "register_operand" "r")))]
  120. - "TARGET_ZBB || TARGET_ZBP"
  121. + "TARGET_ZBB"
  122. { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
  123. [(set_attr "type" "bitmanip")])
  124. @@ -335,7 +335,7 @@
  125. [(set (match_operand:DI 0 "register_operand" "=r")
  126. (rotate:DI (match_operand:DI 1 "register_operand" "r")
  127. (match_operand:QI 2 "register_operand" "r")))]
  128. - "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
  129. + "TARGET_64BIT && TARGET_ZBB"
  130. "rol\t%0,%1,%2"
  131. [(set_attr "type" "bitmanip")])
  132. @@ -343,7 +343,7 @@
  133. [(set (match_operand:DI 0 "register_operand" "=r")
  134. (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  135. (match_operand:QI 2 "register_operand" "r"))))]
  136. - "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
  137. + "TARGET_64BIT && TARGET_ZBB"
  138. "rolw\t%0,%1,%2"
  139. [(set_attr "type" "bitmanip")])
  140. @@ -352,7 +352,7 @@
  141. (define_insn "bswapsi2"
  142. [(set (match_operand:SI 0 "register_operand" "=r")
  143. (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
  144. - "TARGET_ZBB || TARGET_ZBP"
  145. + "TARGET_ZBB"
  146. {
  147. if (TARGET_64BIT)
  148. return TARGET_ZBB ? "rev8\t%0,%1\n\tsrai\t%0,%0,32" : "rev8.w\t%0,%1";
  149. @@ -364,7 +364,7 @@
  150. (define_insn "bswapdi2"
  151. [(set (match_operand:DI 0 "register_operand" "=r")
  152. (bswap:DI (match_operand:DI 1 "register_operand" "r")))]
  153. - "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
  154. + "TARGET_64BIT && TARGET_ZBB"
  155. "rev8\t%0,%1"
  156. [(set_attr "type" "bitmanip")])
  157. @@ -378,50 +378,10 @@
  158. ;;; ??? bmat
  159. -(define_insn "*cmix"
  160. - [(set (match_operand:X 0 "register_operand" "=r")
  161. - (xor:X (and:X (xor:X (match_operand:X 1 "register_operand" "r")
  162. - (match_operand:X 3 "register_operand" "r"))
  163. - (match_operand:X 2 "register_operand" "r"))
  164. - (match_dup 3)))]
  165. - "TARGET_ZBT"
  166. - "cmix\t%0,%2,%1,%3"
  167. - [(set_attr "type" "bitmanip")])
  168. -
  169. ;; ??? Can we do this by using the % communtative constraint?
  170. -(define_insn "*cmix2"
  171. - [(set (match_operand:X 0 "register_operand" "=r")
  172. - (xor:X (and:X (xor:X (match_operand:X 1 "register_operand" "r")
  173. - (match_operand:X 3 "register_operand" "r"))
  174. - (match_operand:X 2 "register_operand" "r"))
  175. - (match_dup 1)))]
  176. - "TARGET_ZBT"
  177. - "cmix\t%0,%2,%3,%1"
  178. - [(set_attr "type" "bitmanip")])
  179. -
  180. ;;; ??? cmov
  181. -(define_insn "*mov<X:mode>cc_ne_bitmanip"
  182. - [(set (match_operand:X 0 "register_operand" "=r")
  183. - (if_then_else:X
  184. - (ne (match_operand:X 1 "register_operand" "r") (const_int 0))
  185. - (match_operand:X 2 "register_operand" "r")
  186. - (match_operand:X 3 "register_operand" "r")))]
  187. - "TARGET_ZBT"
  188. - "cmov\t%0,%1,%2,%3"
  189. - [(set_attr "type" "bitmanip")])
  190. -
  191. -(define_insn "*mov<X:mode>cc_eq_bitmanip"
  192. - [(set (match_operand:X 0 "register_operand" "=r")
  193. - (if_then_else:X
  194. - (eq (match_operand:X 1 "register_operand" "r") (const_int 0))
  195. - (match_operand:X 2 "register_operand" "r")
  196. - (match_operand:X 3 "register_operand" "r")))]
  197. - "TARGET_ZBT"
  198. - "cmov\t%0,%1,%3,%2"
  199. - [(set_attr "type" "bitmanip")])
  200. -
  201. ;;; ??? fs[lr]
  202. (define_insn "*shNadd"
  203. diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
  204. index ca3190b6414..61d1e9d96d8 100644
  205. --- a/gcc/config/riscv/riscv-opts.h
  206. +++ b/gcc/config/riscv/riscv-opts.h
  207. @@ -70,24 +70,12 @@ enum stack_protector_guard {
  208. #define MASK_ZBA (1 << 0)
  209. #define MASK_ZBB (1 << 1)
  210. #define MASK_ZBS (1 << 2)
  211. -#define MASK_ZBP (1 << 3)
  212. -#define MASK_ZBE (1 << 4)
  213. -#define MASK_ZBF (1 << 5)
  214. -#define MASK_ZBC (1 << 6)
  215. -#define MASK_ZBR (1 << 7)
  216. -#define MASK_ZBM (1 << 8)
  217. -#define MASK_ZBT (1 << 9)
  218. +#define MASK_ZBC (1 << 3)
  219. #define TARGET_ZBA ((riscv_bitmanip_subext & MASK_ZBA) != 0)
  220. #define TARGET_ZBB ((riscv_bitmanip_subext & MASK_ZBB) != 0)
  221. #define TARGET_ZBS ((riscv_bitmanip_subext & MASK_ZBS) != 0)
  222. -#define TARGET_ZBP ((riscv_bitmanip_subext & MASK_ZBP) != 0)
  223. -#define TARGET_ZBE ((riscv_bitmanip_subext & MASK_ZBE) != 0)
  224. -#define TARGET_ZBF ((riscv_bitmanip_subext & MASK_ZBF) != 0)
  225. #define TARGET_ZBC ((riscv_bitmanip_subext & MASK_ZBC) != 0)
  226. -#define TARGET_ZBR ((riscv_bitmanip_subext & MASK_ZBR) != 0)
  227. -#define TARGET_ZBM ((riscv_bitmanip_subext & MASK_ZBM) != 0)
  228. -#define TARGET_ZBT ((riscv_bitmanip_subext & MASK_ZBT) != 0)
  229. #define MASK_ZICSR (1 << 0)
  230. #define MASK_ZIFENCEI (1 << 1)
  231. --
  232. 2.33.1