0007-merge-from-riscv-gcc-10.2.0-to-support-bitmanip.patch 4.4 KB

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  1. From 2441e7b302dc5f3805b61b3a675adb80de35fb4b Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Sat, 9 Oct 2021 10:41:17 +0800
  4. Subject: [PATCH 07/15] merge from riscv-gcc-10.2.0 to support bitmanip
  5. ---
  6. gcc/common/config/riscv/riscv-common.c | 32 ++++++++++++++++++++++++++
  7. gcc/config/riscv/riscv-opts.h | 22 ++++++++++++++++++
  8. gcc/config/riscv/riscv.opt | 5 ++++
  9. 3 files changed, 59 insertions(+)
  10. diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
  11. index 34b74e52a2d..c7b6158af4b 100644
  12. --- a/gcc/common/config/riscv/riscv-common.c
  13. +++ b/gcc/common/config/riscv/riscv-common.c
  14. @@ -50,6 +50,16 @@ static const riscv_implied_info_t riscv_implied_info[] =
  15. {"d", "f"},
  16. {"f", "zicsr"},
  17. {"d", "zicsr"},
  18. + {"b", "zbb"},
  19. + {"b", "zbs"},
  20. + {"b", "zba"},
  21. + {"b", "zbp"},
  22. + {"b", "zbe"},
  23. + {"b", "zbf"},
  24. + {"b", "zbc"},
  25. + {"b", "zbm"},
  26. + {"b", "zbr"},
  27. + {"b", "zbt"},
  28. {NULL, NULL}
  29. };
  30. @@ -101,6 +111,17 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
  31. {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
  32. {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
  33. + {"b", ISA_SPEC_CLASS_NONE, 0, 93},
  34. + {"zba", ISA_SPEC_CLASS_NONE, 0, 93},
  35. + {"zbb", ISA_SPEC_CLASS_NONE, 0, 93},
  36. + {"zbc", ISA_SPEC_CLASS_NONE, 0, 93},
  37. + {"zbe", ISA_SPEC_CLASS_NONE, 0, 93},
  38. + {"zbf", ISA_SPEC_CLASS_NONE, 0, 93},
  39. + {"zbr", ISA_SPEC_CLASS_NONE, 0, 93},
  40. + {"zbm", ISA_SPEC_CLASS_NONE, 0, 93},
  41. + {"zbs", ISA_SPEC_CLASS_NONE, 0, 93},
  42. + {"zbt", ISA_SPEC_CLASS_NONE, 0, 93},
  43. + {"zbp", ISA_SPEC_CLASS_NONE, 0, 93},
  44. /* Terminate the list. */
  45. {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
  46. };
  47. @@ -900,10 +921,21 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
  48. {"f", &gcc_options::x_target_flags, MASK_HARD_FLOAT},
  49. {"d", &gcc_options::x_target_flags, MASK_DOUBLE_FLOAT},
  50. {"c", &gcc_options::x_target_flags, MASK_RVC},
  51. + {"b", &gcc_options::x_target_flags, MASK_BITMANIP},
  52. {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
  53. {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
  54. + {"zba", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBA},
  55. + {"zbb", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBB},
  56. + {"zbs", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBS},
  57. + {"zbp", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBP},
  58. + {"zbr", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBR},
  59. + {"zbe", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBE},
  60. + {"zbf", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBF},
  61. + {"zbc", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBC},
  62. + {"zbm", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBM},
  63. + {"zbt", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBT},
  64. {NULL, NULL, 0}
  65. };
  66. diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
  67. index f4cf6ca4b82..ca3190b6414 100644
  68. --- a/gcc/config/riscv/riscv-opts.h
  69. +++ b/gcc/config/riscv/riscv-opts.h
  70. @@ -67,6 +67,28 @@ enum stack_protector_guard {
  71. SSP_GLOBAL /* global canary */
  72. };
  73. +#define MASK_ZBA (1 << 0)
  74. +#define MASK_ZBB (1 << 1)
  75. +#define MASK_ZBS (1 << 2)
  76. +#define MASK_ZBP (1 << 3)
  77. +#define MASK_ZBE (1 << 4)
  78. +#define MASK_ZBF (1 << 5)
  79. +#define MASK_ZBC (1 << 6)
  80. +#define MASK_ZBR (1 << 7)
  81. +#define MASK_ZBM (1 << 8)
  82. +#define MASK_ZBT (1 << 9)
  83. +
  84. +#define TARGET_ZBA ((riscv_bitmanip_subext & MASK_ZBA) != 0)
  85. +#define TARGET_ZBB ((riscv_bitmanip_subext & MASK_ZBB) != 0)
  86. +#define TARGET_ZBS ((riscv_bitmanip_subext & MASK_ZBS) != 0)
  87. +#define TARGET_ZBP ((riscv_bitmanip_subext & MASK_ZBP) != 0)
  88. +#define TARGET_ZBE ((riscv_bitmanip_subext & MASK_ZBE) != 0)
  89. +#define TARGET_ZBF ((riscv_bitmanip_subext & MASK_ZBF) != 0)
  90. +#define TARGET_ZBC ((riscv_bitmanip_subext & MASK_ZBC) != 0)
  91. +#define TARGET_ZBR ((riscv_bitmanip_subext & MASK_ZBR) != 0)
  92. +#define TARGET_ZBM ((riscv_bitmanip_subext & MASK_ZBM) != 0)
  93. +#define TARGET_ZBT ((riscv_bitmanip_subext & MASK_ZBT) != 0)
  94. +
  95. #define MASK_ZICSR (1 << 0)
  96. #define MASK_ZIFENCEI (1 << 1)
  97. diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
  98. index e294e223151..0e73e2ab758 100644
  99. --- a/gcc/config/riscv/riscv.opt
  100. +++ b/gcc/config/riscv/riscv.opt
  101. @@ -136,6 +136,8 @@ Mask(64BIT)
  102. Mask(MUL)
  103. +Mask(BITMANIP)
  104. +
  105. Mask(ATOMIC)
  106. Mask(HARD_FLOAT)
  107. @@ -195,6 +197,9 @@ long riscv_stack_protector_guard_offset = 0
  108. TargetVariable
  109. int riscv_zi_subext
  110. +TargetVariable
  111. +int riscv_bitmanip_subext
  112. +
  113. Enum
  114. Name(isa_spec_class) Type(enum riscv_isa_spec_class)
  115. Supported ISA specs (for use with the -misa-spec= option):
  116. --
  117. 2.33.1