0019-add-four-instruction-for-custom-CSRs.patch 2.9 KB

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  1. From fdda53d94ccaa445c01ead385b85a2b4a5819f11 Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Tue, 6 Sep 2022 01:34:07 -0700
  4. Subject: [PATCH 19/20] add four instruction for custom CSRs
  5. ---
  6. include/opcode/riscv-opc.h | 16 ++++++++++++++++
  7. opcodes/riscv-opc.c | 6 ++++++
  8. 2 files changed, 22 insertions(+)
  9. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  10. index 6f08c72c88..b130357392 100644
  11. --- a/include/opcode/riscv-opc.h
  12. +++ b/include/opcode/riscv-opc.h
  13. @@ -256,6 +256,16 @@
  14. #define MATCH_WFI 0x10500073
  15. #define MASK_WFI 0xffffffff
  16. #define MASK_CUSTOMER_PREF 0x7fff
  17. +/* Custom CSRs instruction */
  18. +#define MATCH_CFLUSH_D_L1 0xfc000073
  19. +#define MASK_CFLUSH_D_L1 0xfff07fff
  20. +#define MATCH_CDISCARD_D_L1 0xfc200073
  21. +#define MASK_CDISCARD_D_L1 0xfff07fff
  22. +#define MATCH_CFLUSH_D_L2 0xfc400073
  23. +#define MASK_CFLUSH_D_L2 0xfff07fff
  24. +#define MATCH_CDISCARD_D_L2 0xfc600073
  25. +#define MASK_CDISCARD_D_L2 0xfff07fff
  26. +/***************************/
  27. #define MATCH_CSRRW 0x1073
  28. #define MASK_CSRRW 0x707f
  29. #define MATCH_CSRRS 0x2073
  30. @@ -2637,6 +2647,12 @@ DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
  31. DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
  32. DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
  33. DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
  34. +/* Custom CSRs instruction */
  35. +DECLARE_INSN(cflush_d_l1, MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1)
  36. +DECLARE_INSN(cdiscard_d_l1, MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1)
  37. +DECLARE_INSN(cflush_d_l2, MATCH_CFLUSH_D_L2, MASK_CFLUSH_D_L2)
  38. +DECLARE_INSN(cdiscard_d_l2, MATCH_CDISCARD_D_L2, MASK_CDISCARD_D_L2)
  39. +/***************************/
  40. DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
  41. DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
  42. DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
  43. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  44. index 5632408ebd..380677e317 100644
  45. --- a/opcodes/riscv-opc.c
  46. +++ b/opcodes/riscv-opc.c
  47. @@ -884,6 +884,12 @@ const struct riscv_opcode riscv_opcodes[] =
  48. {"c.fswsp", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE },
  49. {"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
  50. +/* Custom CSRs instructions. */
  51. +{"cflush.d.l1", 0, INSN_CLASS_ZICSR, "s", MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1, match_opcode, 0 },
  52. +{"cdiscard.d.l1", 0, INSN_CLASS_ZICSR, "s", MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1, match_opcode, 0 },
  53. +{"cflush.d.l2", 0, INSN_CLASS_ZICSR, "s", MATCH_CFLUSH_D_L2, MASK_CFLUSH_D_L2, match_opcode, 0 },
  54. +{"cdiscard.d.l2", 0, INSN_CLASS_ZICSR, "s", MATCH_CDISCARD_D_L2, MASK_CDISCARD_D_L2, match_opcode, 0 },
  55. +
  56. /* Supervisor instructions. */
  57. {"csrr", 0, INSN_CLASS_ZICSR,"d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
  58. {"csrwi", 0, INSN_CLASS_ZICSR,"E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS },
  59. --
  60. 2.25.1