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- From 96138846382f8a6a09cbeb960a928c470dad4df8 Mon Sep 17 00:00:00 2001
- From: Kito Cheng <kito.cheng@sifive.com>
- Date: Tue, 20 Oct 2020 18:14:00 +0800
- Subject: [PATCH 095/107] target/riscv: rvb: rotate (left/right)
- Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
- ---
- target/riscv/insn32-64.decode | 3 +++
- target/riscv/insn32.decode | 3 +++
- target/riscv/insn_trans/trans_rvb.c.inc | 36 +++++++++++++++++++++++++
- target/riscv/translate.c | 36 +++++++++++++++++++++++++
- 4 files changed, 78 insertions(+)
- diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
- index d2daee4a05..52367decc1 100644
- --- a/target/riscv/insn32-64.decode
- +++ b/target/riscv/insn32-64.decode
- @@ -106,9 +106,12 @@ binvw 0110100 .......... 001 ..... 0111011 @r
- bextw 0100100 .......... 101 ..... 0111011 @r
- slow 0010000 .......... 001 ..... 0111011 @r
- srow 0010000 .......... 101 ..... 0111011 @r
- +rorw 0110000 .......... 101 ..... 0111011 @r
- +rolw 0110000 .......... 001 ..... 0111011 @r
-
- bsetiw 0010100 .......... 001 ..... 0011011 @sh5
- bclriw 0100100 .......... 001 ..... 0011011 @sh5
- binviw 0110100 .......... 001 ..... 0011011 @sh5
- sloiw 0010000 .......... 001 ..... 0011011 @sh5
- sroiw 0010000 .......... 101 ..... 0011011 @sh5
- +roriw 0110000 .......... 101 ..... 0011011 @sh5
- diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
- index f0ff5c5441..312a53959e 100644
- --- a/target/riscv/insn32.decode
- +++ b/target/riscv/insn32.decode
- @@ -713,6 +713,8 @@ binv 0110100 .......... 001 ..... 0110011 @r
- bext 0100100 .......... 101 ..... 0110011 @r
- slo 0010000 .......... 001 ..... 0110011 @r
- sro 0010000 .......... 101 ..... 0110011 @r
- +ror 0110000 .......... 101 ..... 0110011 @r
- +rol 0110000 .......... 001 ..... 0110011 @r
-
- bseti 00101. ........... 001 ..... 0010011 @sh
- bclri 01001. ........... 001 ..... 0010011 @sh
- @@ -720,3 +722,4 @@ binvi 01101. ........... 001 ..... 0010011 @sh
- bexti 01001. ........... 101 ..... 0010011 @sh
- sloi 00100. ........... 001 ..... 0010011 @sh
- sroi 00100. ........... 101 ..... 0010011 @sh
- +rori 01100. ........... 101 ..... 0010011 @sh
- diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
- index 44f9f63924..8a46fde476 100644
- --- a/target/riscv/insn_trans/trans_rvb.c.inc
- +++ b/target/riscv/insn_trans/trans_rvb.c.inc
- @@ -179,6 +179,24 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
- return gen_shifti(ctx, a, gen_sro);
- }
-
- +static bool trans_ror(DisasContext *ctx, arg_ror *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_shift(ctx, a, tcg_gen_rotr_tl);
- +}
- +
- +static bool trans_rori(DisasContext *ctx, arg_rori *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_shifti(ctx, a, tcg_gen_rotr_tl);
- +}
- +
- +static bool trans_rol(DisasContext *ctx, arg_rol *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_shift(ctx, a, tcg_gen_rotl_tl);
- +}
- +
- /* RV64-only instructions */
- #ifdef TARGET_RISCV64
-
- @@ -278,4 +296,22 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
- return gen_shiftiw(ctx, a, gen_sro);
- }
-
- +static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_shiftw(ctx, a, gen_rorw);
- +}
- +
- +static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_shiftiw(ctx, a, gen_rorw);
- +}
- +
- +static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_shiftw(ctx, a, gen_rolw);
- +}
- +
- #endif
- diff --git a/target/riscv/translate.c b/target/riscv/translate.c
- index f9dcdf8afe..86f389ba01 100644
- --- a/target/riscv/translate.c
- +++ b/target/riscv/translate.c
- @@ -718,6 +718,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
- tcg_temp_free(t);
- }
-
- +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
- +{
- + TCGv_i32 t1 = tcg_temp_new_i32();
- + TCGv_i32 t2 = tcg_temp_new_i32();
- +
- + /* truncate to 32-bits */
- + tcg_gen_trunc_tl_i32(t1, arg1);
- + tcg_gen_trunc_tl_i32(t2, arg2);
- +
- + tcg_gen_rotr_i32(t1, t1, t2);
- +
- + /* sign-extend 64-bits */
- + tcg_gen_ext_i32_tl(ret, t1);
- +
- + tcg_temp_free_i32(t1);
- + tcg_temp_free_i32(t2);
- +}
- +
- +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
- +{
- + TCGv_i32 t1 = tcg_temp_new_i32();
- + TCGv_i32 t2 = tcg_temp_new_i32();
- +
- + /* truncate to 32-bits */
- + tcg_gen_trunc_tl_i32(t1, arg1);
- + tcg_gen_trunc_tl_i32(t2, arg2);
- +
- + tcg_gen_rotl_i32(t1, t1, t2);
- +
- + /* sign-extend 64-bits */
- + tcg_gen_ext_i32_tl(ret, t1);
- +
- + tcg_temp_free_i32(t1);
- + tcg_temp_free_i32(t2);
- +}
- +
- #endif
-
- static bool gen_arith(DisasContext *ctx, arg_r *a,
- --
- 2.33.1
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