0095-target-riscv-rvb-rotate-left-right.patch 4.8 KB

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  1. From 96138846382f8a6a09cbeb960a928c470dad4df8 Mon Sep 17 00:00:00 2001
  2. From: Kito Cheng <kito.cheng@sifive.com>
  3. Date: Tue, 20 Oct 2020 18:14:00 +0800
  4. Subject: [PATCH 095/107] target/riscv: rvb: rotate (left/right)
  5. Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/insn32-64.decode | 3 +++
  10. target/riscv/insn32.decode | 3 +++
  11. target/riscv/insn_trans/trans_rvb.c.inc | 36 +++++++++++++++++++++++++
  12. target/riscv/translate.c | 36 +++++++++++++++++++++++++
  13. 4 files changed, 78 insertions(+)
  14. diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
  15. index d2daee4a05..52367decc1 100644
  16. --- a/target/riscv/insn32-64.decode
  17. +++ b/target/riscv/insn32-64.decode
  18. @@ -106,9 +106,12 @@ binvw 0110100 .......... 001 ..... 0111011 @r
  19. bextw 0100100 .......... 101 ..... 0111011 @r
  20. slow 0010000 .......... 001 ..... 0111011 @r
  21. srow 0010000 .......... 101 ..... 0111011 @r
  22. +rorw 0110000 .......... 101 ..... 0111011 @r
  23. +rolw 0110000 .......... 001 ..... 0111011 @r
  24. bsetiw 0010100 .......... 001 ..... 0011011 @sh5
  25. bclriw 0100100 .......... 001 ..... 0011011 @sh5
  26. binviw 0110100 .......... 001 ..... 0011011 @sh5
  27. sloiw 0010000 .......... 001 ..... 0011011 @sh5
  28. sroiw 0010000 .......... 101 ..... 0011011 @sh5
  29. +roriw 0110000 .......... 101 ..... 0011011 @sh5
  30. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  31. index f0ff5c5441..312a53959e 100644
  32. --- a/target/riscv/insn32.decode
  33. +++ b/target/riscv/insn32.decode
  34. @@ -713,6 +713,8 @@ binv 0110100 .......... 001 ..... 0110011 @r
  35. bext 0100100 .......... 101 ..... 0110011 @r
  36. slo 0010000 .......... 001 ..... 0110011 @r
  37. sro 0010000 .......... 101 ..... 0110011 @r
  38. +ror 0110000 .......... 101 ..... 0110011 @r
  39. +rol 0110000 .......... 001 ..... 0110011 @r
  40. bseti 00101. ........... 001 ..... 0010011 @sh
  41. bclri 01001. ........... 001 ..... 0010011 @sh
  42. @@ -720,3 +722,4 @@ binvi 01101. ........... 001 ..... 0010011 @sh
  43. bexti 01001. ........... 101 ..... 0010011 @sh
  44. sloi 00100. ........... 001 ..... 0010011 @sh
  45. sroi 00100. ........... 101 ..... 0010011 @sh
  46. +rori 01100. ........... 101 ..... 0010011 @sh
  47. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  48. index 44f9f63924..8a46fde476 100644
  49. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  50. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  51. @@ -179,6 +179,24 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
  52. return gen_shifti(ctx, a, gen_sro);
  53. }
  54. +static bool trans_ror(DisasContext *ctx, arg_ror *a)
  55. +{
  56. + REQUIRE_EXT(ctx, RVB);
  57. + return gen_shift(ctx, a, tcg_gen_rotr_tl);
  58. +}
  59. +
  60. +static bool trans_rori(DisasContext *ctx, arg_rori *a)
  61. +{
  62. + REQUIRE_EXT(ctx, RVB);
  63. + return gen_shifti(ctx, a, tcg_gen_rotr_tl);
  64. +}
  65. +
  66. +static bool trans_rol(DisasContext *ctx, arg_rol *a)
  67. +{
  68. + REQUIRE_EXT(ctx, RVB);
  69. + return gen_shift(ctx, a, tcg_gen_rotl_tl);
  70. +}
  71. +
  72. /* RV64-only instructions */
  73. #ifdef TARGET_RISCV64
  74. @@ -278,4 +296,22 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
  75. return gen_shiftiw(ctx, a, gen_sro);
  76. }
  77. +static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
  78. +{
  79. + REQUIRE_EXT(ctx, RVB);
  80. + return gen_shiftw(ctx, a, gen_rorw);
  81. +}
  82. +
  83. +static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
  84. +{
  85. + REQUIRE_EXT(ctx, RVB);
  86. + return gen_shiftiw(ctx, a, gen_rorw);
  87. +}
  88. +
  89. +static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
  90. +{
  91. + REQUIRE_EXT(ctx, RVB);
  92. + return gen_shiftw(ctx, a, gen_rolw);
  93. +}
  94. +
  95. #endif
  96. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  97. index f9dcdf8afe..86f389ba01 100644
  98. --- a/target/riscv/translate.c
  99. +++ b/target/riscv/translate.c
  100. @@ -718,6 +718,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
  101. tcg_temp_free(t);
  102. }
  103. +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
  104. +{
  105. + TCGv_i32 t1 = tcg_temp_new_i32();
  106. + TCGv_i32 t2 = tcg_temp_new_i32();
  107. +
  108. + /* truncate to 32-bits */
  109. + tcg_gen_trunc_tl_i32(t1, arg1);
  110. + tcg_gen_trunc_tl_i32(t2, arg2);
  111. +
  112. + tcg_gen_rotr_i32(t1, t1, t2);
  113. +
  114. + /* sign-extend 64-bits */
  115. + tcg_gen_ext_i32_tl(ret, t1);
  116. +
  117. + tcg_temp_free_i32(t1);
  118. + tcg_temp_free_i32(t2);
  119. +}
  120. +
  121. +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
  122. +{
  123. + TCGv_i32 t1 = tcg_temp_new_i32();
  124. + TCGv_i32 t2 = tcg_temp_new_i32();
  125. +
  126. + /* truncate to 32-bits */
  127. + tcg_gen_trunc_tl_i32(t1, arg1);
  128. + tcg_gen_trunc_tl_i32(t2, arg2);
  129. +
  130. + tcg_gen_rotl_i32(t1, t1, t2);
  131. +
  132. + /* sign-extend 64-bits */
  133. + tcg_gen_ext_i32_tl(ret, t1);
  134. +
  135. + tcg_temp_free_i32(t1);
  136. + tcg_temp_free_i32(t2);
  137. +}
  138. +
  139. #endif
  140. static bool gen_arith(DisasContext *ctx, arg_r *a,
  141. --
  142. 2.33.1