0070-target-riscv-add-set-round-to-odd-rounding-mode-help.patch 2.8 KB

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  1. From 1fb5a0f3fb0054da1a74e7991b89ecbf0f587452 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Wed, 5 Aug 2020 17:10:50 +0800
  4. Subject: [PATCH 070/107] target/riscv: add "set round to odd" rounding mode
  5. helper function
  6. helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
  7. should be an interface private to translation, so add a new independent
  8. helper_set_rod_rounding_mode().
  9. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  10. ---
  11. target/riscv/fpu_helper.c | 5 +++++
  12. target/riscv/helper.h | 1 +
  13. target/riscv/internals.h | 1 +
  14. target/riscv/translate.c | 5 +++++
  15. 4 files changed, 12 insertions(+)
  16. diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
  17. index 96d7762243..6a054fa1e3 100644
  18. --- a/target/riscv/fpu_helper.c
  19. +++ b/target/riscv/fpu_helper.c
  20. @@ -81,6 +81,11 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
  21. set_float_rounding_mode(softrm, &env->fp_status);
  22. }
  23. +void helper_set_rod_rounding_mode(CPURISCVState *env)
  24. +{
  25. + set_float_rounding_mode(float_round_to_odd, &env->fp_status);
  26. +}
  27. +
  28. static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2,
  29. uint64_t rs3, int flags)
  30. {
  31. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  32. index 51174cdafa..a2a82e92e5 100644
  33. --- a/target/riscv/helper.h
  34. +++ b/target/riscv/helper.h
  35. @@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32)
  36. /* Floating Point - rounding mode */
  37. DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
  38. +DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env)
  39. /* Floating Point - fused */
  40. DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
  41. diff --git a/target/riscv/internals.h b/target/riscv/internals.h
  42. index db105d4d64..065e8162a2 100644
  43. --- a/target/riscv/internals.h
  44. +++ b/target/riscv/internals.h
  45. @@ -43,6 +43,7 @@ enum {
  46. RISCV_FRM_RUP = 3, /* Round Up */
  47. RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
  48. RISCV_FRM_DYN = 7, /* Dynamic rounding mode */
  49. + RISCV_FRM_ROD = 8, /* Round to Odd */
  50. };
  51. static inline uint64_t nanbox_s(float32 f)
  52. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  53. index d10e489cfe..4dfb0a2a51 100644
  54. --- a/target/riscv/translate.c
  55. +++ b/target/riscv/translate.c
  56. @@ -30,6 +30,7 @@
  57. #include "exec/log.h"
  58. #include "instmap.h"
  59. +#include "internals.h"
  60. /* global register indices */
  61. static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
  62. @@ -458,6 +459,10 @@ static void gen_set_rm(DisasContext *ctx, int rm)
  63. return;
  64. }
  65. ctx->frm = rm;
  66. + if (rm == RISCV_FRM_ROD) {
  67. + gen_helper_set_rod_rounding_mode(cpu_env);
  68. + return;
  69. + }
  70. t0 = tcg_const_i32(rm);
  71. gen_helper_set_rounding_mode(cpu_env, t0);
  72. tcg_temp_free_i32(t0);
  73. --
  74. 2.33.1